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1. Hardware Description Language HDL (Hardware Description Language)
The Hardware Description Language (HDL) is a language used to describe digital circuits and systems using formal methods. Designers of digital circuit systems can use this language to describe their design ideas layer by layer (from abstract to concrete) using a series of hierarchical modules to represent extremely complex digital systems. Then, using Electronic Design Automation (EDA) tools, they can perform simulation verification layer by layer, and combine the modules that need to be transformed into specific physical circuits through automatic synthesis tools to convert them into gate-level circuit netlists. Next, specialized integrated circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) can use automatic layout and routing tools to convert the netlists into specific circuit layout structures. Before making physical devices, gate-level models of Verilog (primitive components or UDP) can replace specific basic components. Since its logical function and delay characteristics are completely consistent with real physical components, it can verify the correctness of the physical structure of complex digital systems with the support of simulation tools, achieving a success rate of 100% for wafer fabrication. Currently, this method, known as High-Level Design, has been widely adopted. According to statistics, currently over 90% of ASICs and FPGAs in Silicon Valley, USA, have adopted the Verilog hardware description language method for design.
The development of hardware description languages has a history of nearly thirty years and has been successfully applied in various stages of design: modeling, simulation, verification, and synthesis. In the past decade, the rapid development of synthesis tools that automatically convert synthesizable HDL modules into specific circuits has significantly improved the productivity of complex digital system designs. In advanced electronic industrial countries like the USA and Japan, Verilog has become the foundation for designing digital systems.
Newcomers to FPGA should learn from simple to complex:
(1) Basic syntax of Verilog,
(2) Correspondence between simple synthesizable Verilog modules and logical circuits,
(3) Simple Verilog test modules and their significance,
(4) How to write complex multi-level synthesizable Verilog HDL modules,
(5) How to construct a reliable complex IP soft core and hard core module using synthesizable Verilog modules,
(6) Establishing their FPGA project in development tools to implement simple FPGA examples.
2. History of Verilog HDL
2.1 What is Verilog HDL
Verilog HDL is a type of hardware description language used for digital electronic system design. It allows designers to perform various levels of logical design, enabling simulation verification, timing analysis, and logical synthesis of digital logic systems. It is currently the most widely used hardware description language. According to relevant literature, there are approximately over 100,000 engineers in the USA using Verilog HDL for design, and over 200 universities across the country teach design methods using Verilog hardware description language. In Taiwan, almost all renowned universities’ electronics and computer engineering departments offer courses related to Verilog.
2.2 The emergence and development of Verilog HDL
Verilog HDL was first created in 1983 by Phil Moorby of GDA (GateWay Design Automation) company. Phil Moorby later became the main designer of Verilog-XL and the first partner of Cadence Design Systems. In 1984-1985, Moorby designed the first simulator named Verilog-XL, and in 1986, he made another significant contribution to the development of Verilog HDL by proposing the XL algorithm for fast gate-level simulation.
With the success of the Verilog-XL algorithm, the Verilog HDL language rapidly developed. In 1989, Cadence acquired GDA, making Verilog HDL a proprietary asset of Cadence. In 1990, Cadence decided to open up the Verilog HDL language, establishing the OVI (Open Verilog International) organization to promote the development of Verilog HDL. Due to the superiority of Verilog HDL, IEEE established the IEEE standard for Verilog HDL in 1995, namely Verilog HDL1364-1995; in 2001, the Verilog HDL1364-2001 standard was released; and in 2005, the announcement of the SystemVerilog IEEE 1800-2005 standard greatly improved Verilog’s performance in synthesis, simulation verification, and module reuse.
The following figure illustrates the history and future of Verilog.
Figure 1
2.3 Comparison of Verilog HDL and VHDL
Verilog HDL and VHDL are both hardware description languages used for logical design and have both become IEEE standards. VHDL became an IEEE standard in 1987, while Verilog HDL officially became an IEEE standard in 1995. The reason VHDL became an IEEE standard earlier than Verilog HDL is that VHDL was developed by the US military, while Verilog HDL was converted from a private asset of a common civilian company. Based on the superiority of Verilog HDL, it became an IEEE standard, thus possessing stronger vitality.
VHDL stands for VHSIC Hardware Description Language, where VHSIC is an abbreviation for Very High Speed Integrated Circuit, meaning very high-speed integrated circuits, so the accurate Chinese translation of VHDL is the hardware description language for very high-speed integrated circuits.
As languages for describing hardware circuit designs, both Verilog HDL and VHDL share common characteristics: they can formally abstractly represent the behavior and structure of circuits, support hierarchical and range descriptions in logical design, simplify circuit behavior descriptions using the exquisite structure of high-level languages, possess circuit simulation and verification mechanisms to ensure design correctness, support hierarchical synthesis transformation from high to low levels, are independent of hardware description and implementation processes (process parameters can be included through properties provided by the language), facilitate document management, and are easy to understand and design for reuse.
However, Verilog HDL and VHDL each have their own characteristics. Since Verilog HDL was introduced in 1983 and has over twenty years of application history, it has a broader design community and a much richer resource base than VHDL. The greatest advantage of Verilog HDL compared to VHDL is that it is a very easy-to-master hardware description language. Anyone with a background in C programming can generally master the basic techniques of this design method within two to three months of study and practical operation. Mastering VHDL design techniques is relatively difficult because VHDL is not very intuitive and requires a background in Ada programming. It is generally believed that at least six months of professional training is needed to master the basic design techniques of VHDL. After the announcement of the SystemVerilog IEEE1800-2005 standard in 2005, the integrated circuit design community widely believes that Verilog HDL will completely replace VHDL within ten years, becoming the only language encompassing design, testing, and verification functions in the ASIC design industry. The following Figure 2 shows a comparison of the modeling capabilities of Verilog HDL and VHDL for reader reference:
Figure 2
The Verilog IEEE1364-2001 standard released in 2001 and the SystemVerilog IEEE1800-2005 standard released in 2005 not only significantly improved Verilog’s synthesizable performance and system simulation performance but also made significant breakthroughs in the reuse of IP (including design and verification module reuse). Therefore, Verilog HDL is not only suitable as an entry point and foundation for learning HDL design methods but is also a fundamental technology that ASIC design professionals must master. Learning and mastering Verilog HDL modeling, simulation, synthesis, reuse, and verification techniques can not only provide students with a deeper understanding of digital circuit design technology but also lay a solid foundation for future learning of high-level behavioral synthesis, physical synthesis, IP design, and complex system design and verification.
2.4 Current application status and applicable designs of Verilog
For more than a decade, the EDA community has been debating which hardware description language to adopt in digital logic design. In the past two or three years, the situation in the electronic design communities of the USA, Japan, and Taiwan has clearly shown that Verilog has achieved overwhelming advantages in the field of high-level digital system design; in mainland China, the adoption rate of Verilog has significantly increased in the past ten years. According to my understanding, most integrated circuit design companies in China have adopted Verilog HDL. Verilog was specifically developed for the design and simulation of complex digital systems, making it very suitable for the simulation and synthesis of complex digital logic circuits and systems. Due to Verilog’s strong functionality in describing the underlying gate-level, even the design environments for VHDL are essentially supported by device libraries described by Verilog HDL. The new Verilog HDL standard passed in 1998 incorporated Verilog HDL-A into the new standard, allowing it to support not only the description of digital logic circuits but also the description of analog circuits, thus widely applying it in the design of mixed-signal circuit systems. Today, with deep submicron ASICs and high-density FPGAs becoming mainstream in electronic design, the development prospects of Verilog are very promising. The announcement of the Verilog IEEE1364-2001 standard in March 2001 and the SystemVerilog IEEE 1800-2005 standard in October 2005 significantly improved Verilog’s performance in synthesis, simulation verification, and IP module reuse, further broadening its development prospects.
Verilog is suitable for system-level (System), algorithm-level (Algorithm), register transfer level (RTL), logic level (Logic), gate level (Gate), and circuit switch level (Switch) designs, while SystemVerilog is an extension and elaboration of the Verilog language, making it more suitable for reusable synthesizable IP and reusable verification IP design, as well as very large (over ten million gates) IP-based system-level design and verification.
2.5 Advantages of using Verilog HDL to design complex digital circuits
2.5.1 Traditional design methods – Circuit schematic input method
Decades ago, the design scale of complex digital logic circuits and systems was relatively small and simple. The FPGA or ASIC design work often could only be performed using specialized circuit schematic input tools provided by manufacturers. To meet design performance specifications, engineers often needed to spend several days or longer on tedious manual wiring. Engineers also had to be very familiar with the internal structure and external pin characteristics of the selected devices to meet design requirements. This low-level design method significantly extended the design cycle.
In recent years, FPGA and ASIC designs have continuously progressed in scale and complexity, while the time requirements for logic circuit and system designs have become increasingly shorter. These factors have prompted designers to adopt high-level design tools, such as hardware description languages (Verilog HDL or VHDL) for design.
2.5.2 Comparison between Verilog HDL design method and traditional circuit schematic input method
As described in 2.5.1, designing using the circuit schematic input method has drawbacks such as long design cycles, the need for specialized design tools, and manual wiring. In contrast, using the Verilog input method allows for easy portability of completed designs to different manufacturers’ chips due to the standardization of Verilog HDL. It can also be easily modified for different scales of applications. This is not only because the signal bit width of designs completed using Verilog HDL can be easily changed but also because the simulation test vectors can be completed using the same descriptive language. Additionally, the digital logic generated by Verilog HDL synthesizers is a standard Electronic Design Interchange Format (EDIF) file independent of the implementation process used. The descriptions of the process parameters can be included through properties provided by Verilog HDL, allowing for implementation on different processes’ chips using different manufacturers’ layout and routing tools.
The greatest advantage of using the Verilog input method is its independence from processes. This allows engineers to focus on functional design and logical verification without needing to consider the specific details of gate-level and process implementation too much. They can simply apply different constraints based on the chip requirements during system design to create actual circuits. In practice, this utilizes the immense capabilities of computers and the assistance of EDA tools to separate logical verification from matching specific process libraries and routing and timing calculations into different stages, thereby reducing tedious labor.
2.5.3 Standardization of Verilog
Verilog was first developed successfully by GATEWAY in 1983, and after numerous improvements, it was officially approved as the Verilog IEEE1364-1995 standard in November 1995. In March 2001, based on the original standard, the new Verilog IEEE1364-2001 standard was released after improvements and supplements. In October 2005, the extension of the Verilog language, namely SystemVerilog (IEEE 1800-2005 standard), was launched, significantly improving Verilog’s performance in synthesis, simulation verification, and IP module reuse, further broadening its development prospects.
The standardization of Verilog HDL has greatly accelerated its promotion and development. Due to the process-independent design method of Verilog HDL, the reusability of Verilog models has been significantly enhanced.
2.5.4 Soft Core
A Verilog HDL model that has been verified for functionality, is synthesizable, and has a total gate count of over 5000 gates is referred to as a “soft core.” The devices composed of soft cores are called virtual devices. During the development of new circuits, soft cores and virtual devices can easily combine with other external logic using EDA synthesis tools. This greatly shortens the design cycle and accelerates the design of complex circuits.
2.5.5 Concepts of Hard Core and Soft Core and Their Reuse
2.5.5.1 Hard Core
A coding file of a circuit structure with a total gate count of over 5000 gates that has been verified as correct and is implemented on a specific type of FPGA device is referred to as a “hard core.”
2.5.5.2 Soft Core
A coding file of a circuit structure with a total gate count of over 5000 gates that has been verified as correct and is implemented on a specific type of ASIC device is referred to as a “hard core.”
2.5.5.3 Comparison of Soft Core, Hard Core, and Hard Core
In the logic design stage where the specific implementation methods and process technologies have not yet been determined, soft cores offer the greatest flexibility. They can easily combine with other external logic using EDA synthesis tools. However, due to the uncertainty of implementation technologies, some modifications may be necessary to adapt to the corresponding processes. In comparison, hard cores and soft cores have much less flexibility when combining with other external logic, especially when the circuit implementation process technology changes. The rapid development of circuit implementation process technologies in recent years makes it very necessary to develop soft core design and promote soft core reuse technologies for the accumulation of logic circuit design achievements and to design larger-scale circuits faster and better. Our new generation of digital logic circuit designers must master this knowledge and technology. The Verilog language and its extension SystemVerilog are essential for designing reusable IP, namely soft cores, hard cores, and verification virtual cores.
2.6 FPGA Hardware Description Language Design Process
2.6.1 Top-Down Design
Top-down design begins at the system level, dividing the system into basic units, and then further dividing each basic unit into the next level of basic units until it can be directly implemented using basic components from the EDA component library. Using a hierarchical, structured design method, a complete hardware design task is first divided by the chief designer (Architect) into several operable modules, corresponding models (behavioral or structural) are compiled, and after verification through simulation, these modules are assigned to the next level of designers. This allows multiple designers to design different modules in a hardware system simultaneously, with each designer responsible for their assigned part; the higher-level designer verifies the design completed by the lower-level designer using behavioral-level upper modules. To improve design quality, if some modules can be obtained through commercial channels, we can purchase their intellectual property rights (IP core reuse) to save time and development costs. Figure 3 is a schematic diagram of top-down design, depicted in the form of a design tree.
Figure 3 Top-down Design
2.6.2 Design Compilation and Simulation Process of FPGA Modules
The methods used for designing specific modules at different levels also vary. At high levels, behavioral-level modules are often written and verified through simulation, mainly focusing on the overall performance of the system and the allocation of indicators for each module, rather than the specific implementation of circuits. Therefore, synthesis and subsequent steps often do not need to be performed. However, when the design level is closer to the lower level, behavioral descriptions often need to be implemented using circuit logic. At this point, the modules not only require verification through simulation but also need to undergo synthesis, optimization, layout, and post-simulation. In summary, specific circuits are gradually implemented from the bottom up. EDA tools often support both HDL descriptions and circuit schematic inputs; effectively utilizing these two methods is one way to improve design efficiency. The following flowchart briefly illustrates the module compilation and testing process:
Figure 4
As can be seen from the above figure, the module design process mainly consists of two major functional parts:
(1) Design Development: which includes a series of steps from writing design files –> synthesis to layout and routing –> circuit generation.
(2) Design Verification: which involves a series of steps for various simulations. If problems are found during simulation, modifications are made to the design input.
2.7 Summary
2.7.1 Advantages of Programming Language Verilog
(1) The biggest advantage of using Verilog HDL for circuit design is that it is independent of the process,
(2) It allows for simulation verification of designs at each abstract level,
(3) Verilog HDL is suitable for overall simulation, subsystem simulation, and specific circuit synthesis at all design stages of complex digital logic circuits and systems.
2.7.2 Proficient Mastery of FPGA Design Process
Since the top-down design method starts with system design, performing functional division and structural design from the top level is crucial for overall simulation, which is an important part of functional division. This design is independent of the process. Since the main simulation and debugging processes are completed at a high level, structural design errors can be identified early, avoiding waste in design work, while also reducing the workload of logical simulation. The top-down design method facilitates the division and management of the entire project from the system level, making it possible to design complex digital circuits with scales of hundreds of thousands or even millions of gates, reducing the number of designers, avoiding unnecessary duplicate designs, and improving the success rate of design on the first attempt.
Bottom-up design can be seen as the reverse process of the aforementioned top-down design in a certain sense. Although the design also starts from the system level, specifically from the root of the design tree, the division process must begin with the already existing basic units. The units at the end of the design tree must either be units that have already been manufactured, units that have been developed in other projects, or units that can be purchased externally.
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