A chip typically goes through five major stages and over 20 key steps from “sand” to “power on.” Below is a “high-speed rail timetable” to help you quickly understand the entire industry chain:
Stage1 Design (0→1, turning algorithms into blueprints)
StepCore Tools/OutputOne-sentence Explanation
1. Requirement DefinitionMarket/Customer SpecFirst define“how many Hz, how many cores, power < a few watts”
2. Architecture DesignSystemC/RTLDrawthe “functional block diagram” – who is responsible for computation, who is responsible for storage
3. Front-end DesignVerilog/VHDLWrite the logic of the traffic lights for “every street” in code
4. Functional VerificationSynopsys VCS, Cadence XceliumRun tens of millions of test vectors to ensure the code is free ofbugs
5. Back-end DesignCadence Innovus, Synopsys ICC2“Lay the floor” for logic – place transistors, connect wires, and create clock trees
6. Physical VerificationCalibre DRC/LVSCheck if “line spacing” and “hole-to-hole” violate process rules
7. Sign-off OutputGDSII/OASIS filesGenerate the “photolithography blueprint” to be delivered to the wafer fab
Stage2 Manufacturing (carving the blueprint onto silicon wafers)
StepKey Equipment/MaterialsOne-sentence Explanation
8. Silicon Ingot PullingSingle crystal furnace, polycrystalline silicon materialTransform sand into99.9999999% pure silicon ingots
9. Wafer Slicing and PolishingWire saw, CMPSlice into0.75 mm thick wafers with surface roughness < 0.1 nm
10. Thermal OxidationHigh-temperature furnace tubeGrow a layer ofSiO₂ “insulating paint”
11. Photoresist Coating and ExposureASML EUV, KrF/ArF lithography machines“Photograph” the GDSII pattern onto the resist, with a minimum line width of 3 nm
12. EtchingLam etching machine“Etch” the pattern from the resist into silicon or metal
13. Ion ImplantationIon implantation machineUse “boron/phosphorus bullets” to change the conductivity type of silicon, creating N/P wells
14. Thin Film DepositionAMAT PVD/CVD/ALDDeposit metals and dielectric layers, like“3D printing” layers of buildings
15. Chemical Mechanical PolishingCMP“Polish” the tall buildings flat, preparing for the next layer of photolithography
16. Repeat Steps 10-15500-1000 cyclesAbout 60 layers for the 14 nm node, over 100 layers for the 3 nm node
17. Metal InterconnectionCopper dual damasceneUse copper to “wire” billions of transistors into a complete circuit
Stage3 Packaging and Testing (turning bare chips into solderable “black boxes”)
StepKey EquipmentOne-sentence Explanation
18. Wafer TestingProbe station + ATEFirst filter out“defective” bare chips to avoid subsequent waste
19. DicingDiamond saw bladeCut the 300 mm wafer into thousands of small dies
20. Die BondingDie bonder + wire bonderAttach dies to the substrate, using gold wire to “tie shoelaces”
21. MoldingInjection molding machine + epoxy resinEncapsulate into black “chocolate” – the appearance is the chip we commonly see
22. Final TestingSorting machine + ATERun tests at high temperature/low temperature/high voltage at full speed, marking frequency and grading
Stage4 System Integration (the chip is powered on for the first time)
StepKey OutputOne-sentence Explanation
23. PCB AssemblySMT lineSolder the chip, resistors, and capacitors onto the mainboard
24. Firmware/DriversBIOS/BSPEnable the operating system to “recognize” this new chip
25. System IntegrationMobile phone/server The chip runs a complete operating system for the first time, such as Android or Linux
Stage5 End-User Usage & Feedback (data feedback)
StepKey ActionsOne-sentence Explanation
26. Field OTACloud patchesSmall bugs can be “patched” through software
27. Failure AnalysisFA laboratoryAnalyze “frozen” chips returned by users to determine if the issue is design or manufacturing-related
28. Design IterationNext generationSpecFeed back on-site data to Stage 1 for iterative upgrades
A summary in one image (save it for reference)
Sand → Silicon Ingot → Wafer → Photolithography → Etching → Ion Implantation → Thin Film → CMP → Multi-layer Interconnection → Testing → Dicing → Packaging → Final Testing → Mainboard → Complete System → User → Data Feedback
Key Takeaway
The three major stages of design, manufacturing, and packaging can be physically separated— thus the birth of the fabless model.
Manufacturing is the most capital-intensive: A $20 billion investment for a 3 nm fab accounts for 55% of the entire industry chain cost.
EDA + IP + equipment are the “bottleneck” concentration areas – the U.S. control list mainly targets steps 4, 11, 12, and 13.
The packaging stage in mainland China has surpassed38% of the global market share, but high-end packaging (2.5D/3D) is still dominated by TSMC and ASE.