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Core Insights
Market Overview
In the past week (August 4-8), the SW Electronics Index rose by 1.65%, outperforming the CSI 300 Index by 0.42 percentage points. Among the six major sub-sectors, the performance of consumer electronics, other electronics II, electronic chemicals II, optical optoelectronics, semiconductors, and components were 4.27%, 4.06%, 2.70%, 1.51%, 1.45%, and -1.59%, respectively.
Core Insights
■ The AI boom is emerging, and CoWoP is expected to become the next-generation chip packaging technology, benefiting PCB manufacturing, material supply, and equipment segments.According to Ai Jiwei, recent news indicates that NVIDIA is considering integrating CoWoP into the next-generation Rubin GPU, with CoWoP being regarded as the next advanced packaging solution following CoWoS.
■ CoWoS is a 2.5D advanced packaging technology led by TSMC, breaking through the bandwidth and energy efficiency bottlenecks of traditional packaging.
Types of CoWoS:CoWoS (Chip On Wafer On Substrate) can be categorized into three main types based on different interposer types: CoWo-S, CoWoS-L, and CoWo-R. Among them, CoWo-S has the highest maturity and is suitable for current mainstream AI chip demands; CoWoS-L is the core process for future high-performance GPUs; CoWo-R is aimed at ultra-large-scale integration scenarios with strong technological foresight.
CoWoS Application Scenarios:Currently, the application scenarios for CoWoS packaging are highly focused on high computing power demand areas, with core application fields including AI computing chips, HBM storage integration, and cloud computing ASICs.
CoWoS Demand and Capacity Scale:Currently, the supply of CoWoS capacity is insufficient, and it is expected to reach balance by 2026. In 2024, TSMC’s CoWoS monthly capacity is projected to be 35,000-40,000 wafers, with a target increase to 70,000-80,000 wafers per month in 2025, and plans to further increase to 150,000 wafers per month by 2028.
■ CoWoP technology evolves from the current CoWoS, representing the next-generation advanced packaging solution.
Core of CoWoP Design:According to Semiconductor Industry Insights, CoWoP (Chip on Wafer on PCB) technology evolves from the current mainstream 2.5D integration technology CoWoS, focusing on eliminating the ABF packaging substrate and directly bonding the silicon interposer to high-density PCBs.
Advantages of CoWoP:By removing the ABF substrate, losses can be reduced, significantly enhancing the coverage and stability of high-speed interconnects such as NVLink; optimizing power efficiency; and eliminating the packaging lid and substrate allows heat to be directly conducted to the heat sink, enhancing cooling efficiency.
Beneficiaries of the CoWoP Supply Chain:According to Ai Jiwei, on one hand, it benefits companies in the PCB manufacturing segment; manufacturers with advanced mSAP capabilities and familiarity with substrate/packaging processes are expected to seize opportunities; on the other hand, material supply and equipment testing segment manufacturers are expected to benefit, with materials including electronic fabrics, peelable copper foils, etc.
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Risk Warning
Technological development may not meet expectations, intensified US-China trade frictions, terminal demand may not meet expectations, and domestic substitution may not meet expectations.
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Report Source
Report Title: “Next-Generation CoWoP Chip Packaging Technology: PCB Manufacturing, Material Supply, and Equipment Segments Expected to Benefit – Electronics Industry Weekly Report (2025.08.04-2025.08.08)”
Analyst: Fang Chen
Tel: 021-53686475
E-mail: [email protected]
SAC Number: S0870523060001
Report Release Date: August 11, 2025
Published by: Shanghai Securities Co., Ltd.
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Disclaimer
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