In the semiconductor industry, as processes continue to shrink to 3nm, 2nm, and even smaller sizes, the complexity of analog and mixed-signal circuits is increasing exponentially. FinFET, multi-power domain architectures, and analog-digital co-design have become mainstream, but traditional simulation and rule-based verification tools are increasingly inadequate. Design teams are forced to spend weeks sifting through Electrical Rule Check (ERC) reports, still struggling to cover all corner cases, leading to re-tape-out risks, product delays, and even reliability issues.
Founded in 2019, the French EDA company Aniah is dedicated to addressing this core pain point in the industry. Its founder and CEO, Vincent Bligny, has accumulated extensive experience in analog design, transistor-level verification, and advanced process chip system architecture at STMicroelectronics. He keenly observed that the industry needs a method capable of exhaustive verification directly at the transistor level, ensuring design correctness under all potential electrical states without relying on test vectors.
OneCheck: A Revolutionary Tool for Transistor-Level Electrical Rule Checking
Aniah’s core product, OneCheck, is a static analysis tool aimed at transistor-level Electrical Rule Checking (ERC). Its uniqueness lies in its use of vector-less verification methods, which can perform exhaustive analysis on complete chip netlists, covering all voltage domains, power states, and signal interaction structures.
Compared to traditional simulation, OneCheck can detect electrical states that are difficult to trigger in dynamic simulations but pose real risks, such as:
- •
Unexpected conduction paths
- •
Floating nodes
- •
Improper cross-voltage domain connections
- •
Power timing dependency violations
- •
Illegal level-shifting topologies
Key Advantages
Comprehensive Coverage: Even in SoCs with thousands of power states, all transistor-level error conditions can be exhaustively covered.
High Computational Efficiency: Designs with approximately 10 million transistors can be analyzed in seconds, while designs with billions of transistors can be completed in minutes.
Low False Positive Rate: By utilizing root-cause clustering technology, the analysis and judgment costs are significantly reduced.
Production Verification Records
OneCheck has been validated on multiple advanced process nodes, including:
- •
TSMC A16 (1.6nm)
- •
3nm/5nm/16nm FinFET
- •
BCD and high-voltage mixed-signal processes
This tool is widely used in critical analog and mixed-signal modules, such as PLL/DLL/clock circuits, DDR/LP/IO PHY interfaces, PMIC power regulation networks, GPIO multi-voltage domain interfaces, and high-speed SerDes I/O.
Currently, leading global GPU/AI accelerator chip manufacturers, mobile SoC design companies, display driver manufacturers, and power management IC vendors (all top ten design companies) have incorporated OneCheck into their formal design processes.
Performance Data Proves Strength
According to actual operational data, OneCheck demonstrates outstanding performance across circuits of different scales:
|
Circuit Type |
Scale |
Run Time |
Power Scenarios |
False Positive Reduction |
|---|---|---|---|---|
|
Automotive Electronics |
2 million transistors |
2 seconds |
12,000 |
1000 times |
|
Mixed-Signal Sensors |
20 million transistors |
2 seconds |
130 |
200 times |
|
Low-Power SoC (FDSOI) |
200 million transistors |
3 minutes |
200,000 |
100 times |
|
Multi-Core CPU |
6 billion transistors |
10 minutes |
50 |
5 times |
Smart network analysis technology has further reduced the false positive rate by 94%-100%, such as reducing domain cross errors in an image sensor from 50,630 to 210, achieving a reduction of 99.5%.
Amigo AI: Next-Generation Intelligent Agent for Analog Design Review
Although OneCheck achieves transistor-level electrical correctness verification, the design review of analog circuits still heavily relies on engineer experience. To address this, Aniah is developing Amigo AI—a smart collaborative agent for analog circuit design review, expected to release its first version in December 2025.
The core goal of Amigo AI is not to replace engineers but to enhance their review efficiency and decision accuracy. It learns from the team’s existing design intent patterns, review results, and ERC repair strategies, combined with the graphical structure representation of circuit diagrams, to achieve:
- •
Classification and root cause analysis of OneCheck violation results
- •
Repair strategy suggestions for problematic topologies
- •
Natural language explanations of repair reasons and circuit impacts
- •
Continuous learning through a “reject → suggest alternative repair → final confirmation” cycle
- •
Formation of a transferable design knowledge base within the team
The first version will focus on supporting automatic exemption classification, repair pattern recommendations, and explanation engine functions. By combining OneCheck’s deterministic correctness with Amigo AI’s learnable reasoning capabilities, Aniah is building a closed-loop design verification and review system, expected to help teams reduce design review and debugging time by 30-80%.
Global Layout and Industry Vision
Aniah’s strategic layout in France, Taiwan, and the United States reflects its unique positioning in the global semiconductor ecosystem: France provides theoretical research and model innovation capabilities; Taiwan has a leading global wafer manufacturing and analog/mixed-signal design ecosystem; the United States promotes system architecture, AI, and high-performance computing Chiplet integration development.
Aniah not only provides tools but also establishes a new verification framework connecting design methodologies, process requirements, and system reliability criteria, helping engineering teams achieve true First-Time-Right in advanced processes and high-complexity SoC environments.
As the semiconductor industry moves towards smaller nodes and more complex architectures, Aniah’s transistor-level verification technology is becoming a key engine for ensuring chip reliability and shortening time-to-market, providing a solid foundation for global semiconductor innovation.