Embedded C Language – Computer Architecture and CPU Operation Principles

The core of computer architecture lies inthe instruction set which defines “what to do,”the microarchitecture determines “how to do it,”the packaging and bus decide “how to connect,”the memory hierarchy determines “how fast to access data,”and parallelism and dedicated units determine “how much can be done.” From the Turing machine to modern SoCs, all complex computations can be reduced to combinations of a finite set of instructions, and the evolution of architecture is the continuous process of accelerating these combinations with hardware.

1. Hardware Packaging and Integration Levels

1. DIP (Dual In-line Package)

• Traditional dual in-line package with fewer pins, suitable for early CPUs and memory chips, facilitating manual soldering and prototype development.

CSP (Chip Scale Package)

• Chip-level packaging where the package size is nearly equal to the die area, reducing parasitic effects and improving high-frequency performance, widely used in mobile SoCs.

SoC (System on Chip)

• Integrates CPU, GPU, DSP, NPU, I/O controllers, Cache, buses, etc., into a single silicon chip, forming a complete computing system.

2. Instruction Set and Microarchitecture

1. Instruction Set (ISA)

• Function: Defines instruction formats, operand types, register allocation, addressing modes, byte order (big-endian/little-endian), and byte alignment.

• Typical Instructions: Addition, subtraction, multiplication, AND, OR, NOT, shifting, jumping, Load/Store, etc.

• Load/Store Architecture: Operation instructions only manipulate registers, while memory access is completed through separate Load/Store instructions, simplifying the pipeline.

Microarchitecture

• Branch Prediction: Reduces pipeline stalls and improves IPC (Instructions Per Cycle).

• Dispatch Strategy: Single dispatch, superscalar multiple dispatch (VLIW / Out-of-Order).

• Execution Order: In-order execution (simple, low power) vs. out-of-order execution (high performance).

• Pipeline Depth: The deeper the pipeline, the higher the clock frequency, but branch penalties and power consumption increase.

• Cache Hierarchy: L1 (instruction + data), L2 (private or shared), L3 (shared among multiple cores), balancing capacity and latency.

3. Storage and Address Models

Model	Instruction/Data Storage	Access Method	Example Scenarios
Von Neumann	Unified Storage	Serial	General PCs, external buses of microcontrollers
Harvard	Separate Storage	Parallel	Microcontroller core Cache, DSP
Hybrid	On-chip Harvard Cache + off-chip Von Neumann	SoC Internal high-speed cache + External DDR

• Unified Addressing: RAM and peripheral registers share the address space (ARM, x86).

• Independent Addressing: Memory and peripheral address spaces are separate (early 8051).

4. Cache Mechanism

1. Working Principle

• Loads according toCache Line (e.g., 64 B), utilizing spatial locality.

• Write strategies: Write-back and Write-through.

• Replacement strategies: LRU, random, pseudo LRU.

Multi-level Topology

• Single-core: L1-I + L1-D → L2 (private).

• Multi-core: Each core has private L1/L2 → shared L3 (ring bus or mesh).

• Consistency: MESI/MOESI protocol.

5. Pipeline Stages

1. Classic Five Stages Instruction Fetch (IF) → Instruction Decode (ID) → Execute (EX) → Memory Access (MEM) → Write Back (WB).

2. Hazard Handling

• Structural Hazard: Register renaming, adding hardware resources.

• Data Hazard: Forwarding, stall.

• Control Hazard: Branch prediction (static/dynamic), delay slots, speculative execution.

Out-of-Order Execution

• Reorders instruction sequence to eliminate stalls and increase parallelism.

• Reorder Buffer (ROB) ensures results are committed in order.

6. Parallel Computing and Multi-core Technology

Technology	Description	Example
SIMD	Single Instruction Multiple Data, vector operations	SSE/AVX/NEON
Big.LITTLE	big.LITTLE architecture, using big Cluster for high load and LITTLE Cluster for light load	ARM Cortex-A78+A55
Hyper-Threading	4 cores 8 threads, logical cores share execution units	Intel Hyper-Threading

7. Overview of Dedicated Processing Units

Abbreviation	Full Name	Main Use
CPU	Central Processing Unit	General computation, control
GPU	Graphics Processing Unit	Graphics rendering, large-scale parallel computing
FPGA	Field Programmable Gate Array	Reconfigurable logic, prototyping
DSP	Digital Signal Processor	Real-time signal processing
TPU	Tensor Processing Unit	Google AI inference acceleration
NPU	Neural Processing Unit	Edge AI, deep learning
APU	Accelerated Processing Unit	AMD CPU+GPU fusion
BPU	Horizon AI Chip	Autonomous driving
DPU	Deep Learning Processing Unit	Data center AI
EPU	Emotion Processing Unit	Robot emotion synthesis
FPU	Floating Point Unit	Floating point operations within processors
HPU	Holographic Processing Unit	Microsoft HoloLens
IPU	Intelligent Processing Unit	Graphcore AI
KPU	Kanan Yunzhi AI	Edge computing
OPU	Optical Flow Processing Unit	Computer vision
VPU	Video Processing Unit	Video encoding/decoding
WPU	Wearable Processing Unit	Wearable devices
XPU	Baido FPGA Cloud Acceleration	256-core AI cloud
ZPU	Zylin Open Source Processor	32-bit open-source soft core

8. Instruction Lifecycle (Micro-operation Level)

1. Prefetch: Fetch instructions from L1-I Cache based on PC value.

2. Decode: The decoder splits the instruction into micro-operations (μop).

3. Dispatch: The scheduler dispatches μop to functional units (ALU, FPU, LSU).

4. Execute: Functional units complete computation or memory access.

5. Write Back: Results are written back to registers or Cache.

Register Bypass: Execution results are directly bypassed to subsequent instructions to avoid write-back stalls.Address Calculation: Base + offset + scaling factor, supporting byte alignment and boundary alignment checks.

9. Byte Order and Alignment

• Big-endian: High-order byte at low address (network protocols).

• Little-endian: Low-order byte at low address (x86, ARM).

• Byte Alignment: Addresses are multiples of data width, improving access efficiency.

10. Performance Determinants

Factor	Impact Dimension
Pipeline Depth	Frequency ↑, branch penalty ↑
Clock Frequency	Theoretical throughput ↑, power consumption ↑
Cache Capacity	Hit rate ↑, latency ↓
Branch Prediction	Pipeline stalls ↓, IPC ↑
Out-of-Order Execution	Parallelism ↑, complexity ↑