In ARM-based MCU subsystems, there are only 240 peripheral interrupts available. Therefore, for a large number of interrupts, a secondary lookup is necessary. The cost of this approach is that it cannot achieve timely system responses, as it requires time to read the status registers.This article introduces the method of compressing interrupt signals and the implementation of secondary interrupt lookup.

1. Interrupt Signal Compression (First Level)

Method: Logically “OR” multiple interrupt signals together while retaining their individual interrupt states.

Hardware Implementation:assign combined_irq = irq_source1 | irq_source2 | … | irq_sourceN;

RO (Read-Only) Status Register:

The status (triggered or not) of each interrupt source will still be recorded in the RO (Read-Only) register.For example:RO_STATUS_REG = { irq_sourceN, …, irq_source2, irq_source1 }

Even if multiple interrupts are merged into one combined_irq, the software can still distinguish which specific interrupt was triggered by querying the RO_STATUS_REG.

2. Secondary Interrupt Lookup (Second Level)

Method: In the ISR (Interrupt Service Routine), the specific interrupt source is distinguished by querying the CSR (Control & Status Register).

Process:

The CPU receives combined_irq and enters the general ISR.The ISR reads the RO_STATUS_REG to check which interrupt sources have been triggered.Based on the value of RO_STATUS_REG, it jumps to the corresponding sub-ISR to handle the specific interrupt.Clears the interrupt status (if necessary, write to CSR to clear the interrupt flag).

Example

void combined_irq_handler() {

uint32_t status = read_csr(RO_STATUS_REG); // Read interrupt status    if (status & (1 << IRQ_SOURCE1)) {    irq_source1_handler(); // Handle IRQ_SOURCE1    clear_irq(IRQ_SOURCE1); // Clear interrupt flag}if (status & (1 << IRQ_SOURCE2)) {    irq_source2_handler(); // Handle IRQ_SOURCE2    clear_irq(IRQ_SOURCE2);}// … Other interrupt sources}

Advantages:

Reduces the number of interrupt lines (hardware savings).Maintains flexibility (software can still distinguish specific interrupt sources).Suitable for merging low-priority interrupts (e.g., multiple peripherals sharing one interrupt line).

Applicable Scenarios:

SoC design (multiple peripherals sharing interrupt lines).Embedded systems (limited interrupt resources but need to distinguish multiple events).RISC-V / ARM Cortex-M (similar interrupt management method to NVIC).

This way, the number of interrupts is compressed while still allowing precise identification of interrupt sources at the software level, improving system efficiency.