Comparison and Technical Roadmap of RISC-V AI Chip SoC Architectures

1. Overview of the RISC-V AI Chip Market in Data Centers

1.1 Current Market Development and Trends

Currently, RISC-V AI chips are experiencing historic development opportunities in the data center sector. According to industry data, the growth rate of RISC-V chips in China reaches 20%-30%, far exceeding the growth rates of other architecture chips. The RISC-V International Foundation expects to have 5,000 member units by the end of 2025, and the RISC-V Working Group under the guidance of the Ministry of Industry and Information Technology is expected to have 400 units by the end of 2025. Chinese companies are evolving the RISC-V architecture in sync with foreign enterprises.

In terms of market size, the shipment of RISC-V chips is expected to grow from 80 billion units in 2025 to 162 billion units by 2030, with revenue exceeding $92 billion and a compound annual growth rate of over 70% in the AI sector. In the data center field, heterogeneous computing-based hybrid accelerators (including CPU, GPU, FPGA, and ASIC) are expected to dominate by 2027.

1.2 Major Manufacturers and Product Landscape

In the field of RISC-V AI chips for data centers, major manufacturers present a diversified competitive landscape:

International Manufacturers: SiFive, as a leading enterprise in the RISC-V ecosystem, will launch the second generation of its Intelligence series processor IP in September 2025, including the new X100 series (X160 Gen 2 and X180 Gen 2) and upgraded X280 Gen 2, X390 Gen 2, and XM Gen 2, covering high-performance applications from edge to data center. Ventana Micro Systems’ Veyron V2 platform, recognized as the highest performance RISC-V processor in the industry, began shipping in 2025, supported by leading hyperscale data centers and HPC customers in the Americas, Europe, and Asia.

Domestic Manufacturers: Alibaba’s T-Head has formed a complete product matrix from the E series, R series to the C series, with the Xuantie C930 being the first server-grade RISC-V CPU, boasting a clock speed of up to 3.4GHz and achieving a SPECint2006 benchmark score of 15.2/GHz, equipped with 512 bits RVV1.0 and 8 TOPS Matrix dual engines. The K1 chip from Jintide Shikong, an 8-core RISC-V AI CPU, has exceeded 50,000 units in cumulative mass production delivery by December 2024, making it the fastest mass-produced RISC-V high-performance chip. Sifang Technology released its first data center management chip “Lion Mountain Chip” based on the RISC-V architecture in November 2025, successfully achieving the first large-scale commercial deployment of RISC-V in the data center field.

1.3 Demand Characteristics of Data Center Scenarios

Data center scenarios have unique and stringent demand characteristics for AI chips, mainly reflected in the following aspects:

High Performance Requirements: Data centers need to handle large-scale AI training and inference tasks, requiring chips to have strong computing power density. For example, when processing large models with hundreds of billions of parameters, chips need to provide hundreds of TFLOPS or even higher computing power.

High Energy Efficiency Ratio Requirements: The energy consumption cost of data centers accounts for a significant proportion of operating costs, thus there are extremely high requirements for the energy efficiency ratio of AI chips. According to industry data, advanced RISC-V AI chips can achieve energy efficiency ratios of 300-800 GOPS/W.

Large-Scale Scalability: Data centers typically need to build large-scale AI computing clusters, which requires chips to have good scalability and interconnect capabilities. For example, Huawei’s Ascend 910C can scale to a 160,000 card cluster through CloudMatrix384 super node technology, with linearity exceeding 95%.

Memory Bandwidth Requirements: AI workloads have extremely high memory bandwidth requirements, especially when processing large models. HBM2E memory can provide bandwidth of up to 3.2TB/s, while DDR5 memory has a single channel bandwidth of about 70-100GB/s.

Software Ecosystem Compatibility: Data centers need to be compatible with existing AI software ecosystems, including mainstream frameworks such as TensorFlow, PyTorch, and ONNX. Most RISC-V AI chips are striving to achieve seamless integration with these frameworks.

2. Comparative Analysis of Mass-Produced RISC-V AI Chip SoC Architectures

2.1 Comparison of Technical Specifications of Mainstream Mass-Produced Products

Based on collected information, the following is a comparison table of the technical specifications of major mass-produced RISC-V AI chips:

Product Model	Manufacturer	Process Technology	Core Configuration	Clock Speed	Memory Type	Memory Capacity	Memory Bandwidth	Computing Performance	Power Consumption
Xuantie C930	Alibaba T-Head	12nm	8 Cores	3.4GHz	DDR4	Up to 32GB	–	8 TOPS Matrix	–
Jintide Shikong K1	Jintide Shikong	12nm	8 Cores	1.5GHz	LPDDR4X	8GB	–	2 TOPS	–
Sifang “Lion Mountain Chip”	Sifang Technology	28nm	4 Cores	1.8GHz	DDR4	16GB	–	Supports AI Inference	–
SiFive X280 Gen 2	SiFive	7nm	8 Cores	2.5GHz	DDR4	Up to 64GB	–	512-bit Vector	–
Ventana Veyron V2	Ventana	7nm	32 Cores	3.2GHz	DDR5	Up to 2TB	1TB/s	–	300W
Hanguang 800	Alibaba T-Head	12nm	4 NPU Cores	1.8GHz	HBM2	64GB	900GB/s	825 TOPS (INT8)	276W
Cambricon SiYuan 590	Cambricon	7nm	–	–	HBM2e	64GB	–	256 TOPS (FP16)	–
Suiyuan Cloud T20	Suijuan Technology	7nm	–	–	HBM2e	64GB	–	200 TOPS (FP16)	–
MuXi Cloud C500	MuXi	7nm	–	–	HBM2e	80GB	3.35TB/s	300 TOPS (FP16)	–
Huawei Ascend 910C	Huawei HiSilicon	7nm	4 NPU Cores	–	HBM3e	64GB	3.2TB/s	352 TOPS (FP16)	–

2.2 In-Depth Analysis of Memory Architecture

Memory architecture is one of the key factors affecting the performance of RISC-V AI chips, with different manufacturers adopting differentiated design strategies:

HBM High-Bandwidth Memory Solutions: High-end AI chips generally adopt HBM technology, such as Huawei’s Ascend 910C which uses HBM3e memory with a single chip configuration of 64GB and a bandwidth of up to 3.2TB/s. Hanguang 800 uses HBM2 memory, providing a bandwidth of 900GB/s. HBM technology achieves extremely high memory bandwidth through 3D stacked DRAM chips and through-silicon vias (TSV), making it particularly suitable for the data-intensive characteristics of AI workloads.

DDR Memory Solutions: Mid-range and low-end products often use DDR memory, such as Xuantie C930 which supports DDR4 memory with a maximum capacity of 32GB. Ventana Veyron V2 supports DDR5 memory with a maximum capacity of 2TB, providing a bandwidth of 1TB/s. The advantage of DDR memory lies in its lower cost and mature technology, but its bandwidth is relatively limited.

Hybrid Memory Architecture: Some innovative products adopt hybrid memory designs, such as Qualcomm’s AI200/AI250 rack solutions which use LPDDR mobile memory, providing up to 768GB of “near-memory” capacity. This design provides large memory support while reducing power consumption.

On-Chip Storage Optimization: In addition to external memory, on-chip storage design is also crucial. For example, the Occamy system integrates 241MB of on-chip SRAM memory, and Tenstorrent Blackhole has 241MB of on-chip SRAM. These large-capacity on-chip storages can reduce access to external memory and improve data processing efficiency.

2.3 Evaluation of Computing Performance and AI Acceleration Capabilities

In terms of computing performance, different RISC-V AI chips exhibit differentiated capability characteristics:

General Computing Performance: Xuantie C930 achieved a SPECint2006 benchmark score of 15.2/GHz, marking that RISC-V processors are approaching the level of ARM flagship chips in general computing performance. Ventana Veyron V2, as the highest performance RISC-V processor in the industry, can compete with the latest x86 and ARM processors.

AI Acceleration Performance: In terms of AI-specific performance, the chips show significant differences. Hanguang 800’s INT8 computing power reaches 825 TOPS, with INT16 computing power at 205 TOPS, achieving an inference performance of 78,563 IPS in the ResNet-50 model test, with an energy efficiency ratio of 500 IPS/W. Huawei’s Ascend 910C has a single-chip computing power of 352 TOPS (FP16), which can be scaled to a 160,000 card cluster through CloudMatrix384 technology.

Energy Efficiency Ratio Performance: RISC-V AI chips demonstrate significant advantages in energy efficiency ratios. The DARKSIDE system achieved a peak integer performance of 65 GOPS and an energy efficiency ratio of 835 GOPS/W under a 65nm process. The 3D-CIM technology from Micronano Core achieves a 4-fold increase in computing power density and a 5-10 times improvement in energy efficiency through a compute-storage integrated architecture.

Vector and Matrix Extensions: RISC-V provides AI acceleration capabilities through vector extensions (RVV) and matrix extensions. Xuantie C930 is equipped with 512 bits RVV1.0 and 8 TOPS Matrix dual engines, combining general high-performance computing power with native AI computing power. Xuantie C908X supports 4096 bits ultra-long data width RVV1.0 vector extension, allowing a single instruction to process 512 8-bit integers or 128 32-bit floating-point numbers simultaneously.

2.4 Analysis of Adaptability to Typical Application Scenarios

Different RISC-V AI chips exhibit significant differentiated characteristics in application scenario adaptability:

Cloud AI Training Scenarios: High-end products such as Huawei’s Ascend 910C and MuXi Cloud C500 are mainly aimed at large-scale AI training scenarios in the cloud. These chips typically have strong computing power, high-bandwidth memory, and good scalability, capable of supporting training tasks for large models with hundreds of billions of parameters.

Cloud Inference Scenarios: Products like Hanguang 800 and Cambricon SiYuan 590 focus on cloud inference applications. Hanguang 800 has been deployed at scale in Alibaba Cloud data centers, providing computing power support for internal businesses. These chips have been optimized for energy efficiency ratios and inference latency.

Edge Computing Scenarios: Products like Jintide Shikong K1 and Xuantie C908X are mainly aimed at edge AI computing scenarios. Jintide Shikong K1 has completed mass production applications in various industries such as industrial, power, robotics, telecommunications, and consumer electronics. These chips typically have lower power consumption, making them suitable for deployment in resource-constrained edge environments.

Data Center Management Scenarios: Sifang Technology’s “Lion Mountain Chip” is specifically designed for data center management scenarios, serving as the “property management hub” of the data center, fully responsible for system security, energy consumption scheduling, and operation management. This chip has reached cooperation with Super Fusion and will be widely used in AI servers, edge computing, and smart energy scenarios.

3. Chip Technology Roadmap in Prototype Design and R&D

3.1 Characteristics of Cutting-Edge Prototype Design Technologies

In the prototype design phase, RISC-V AI chips exhibit several cutting-edge technological innovations:

Compute-Storage Integrated Architecture: The 3D Compute-Storage Integrated (3D-CIM™) architecture pioneered by Micronano Core integrates three technologies: “3D Near-Memory + In-Memory Computing + RISC-V Compute-Storage,” breaking the impossible triangle of “high performance + low power + low cost.” This technology completes computation within the memory through SRAM compute-storage integration + DRAM 3D stacking, fundamentally eliminating data transport overhead and is seen as a core path for continuing computing power growth in the post-Moore era.

Ultra-Heterogeneous Computing Architecture: The Occamy system adopts a dual-chip design with 432 cores, integrating 768-DP-GFLOP/s computing power, equipped with dual HBM2E memory, supporting 8 to 64-bit dense and sparse computing. This system is realized under a 12nm FinFET process, with each chip containing 24 computing clusters, a host supporting Linux, 16GiB HBM2E DRAM, and a fully digital die-to-die link.

Large-Scale Multi-Core Integration: Tenstorrent’s Blackhole AI chip integrates 768 RISC-V cores, including 16 Big RISC-V cores and 752 Baby RISC-V cores, with the 752 Baby cores integrated into 140 Tensix AI computing cores, providing 745 TFLOPS of FP8 performance.

Near-Data Computing Architecture: The DARKSIDE system adopts a heterogeneous RISC-V computing cluster design, containing 8 enhanced RISC-V cores, supporting mixed precision integer operations from 2 bits to 32 bits, and integrates three dedicated digital accelerators: Deep Convolution Engine (DWE), low-overhead data mover, and 16-bit floating-point tensor product engine (TPE).

3.2 Next-Generation Product Technology Roadmap

According to the technology roadmaps published by various manufacturers, future RISC-V AI chips will exhibit the following development trends:

2025-2026 Technology Roadmap:

• Five products from SiFive’s second-generation Intelligence series have been opened for licensing, with the first chip expected to launch in the second quarter of 2026

• Jintide Shikong’s third-generation flagship RISC-V AI CPU chip based on the “Xiangshan” (Kunming Lake) self-developed X200 core is expected to enter mass production by the end of 2026

• Lingrui Zhixin’s first product, the P100 high-performance RISC-V CPU core, has entered the final sprint stage of development, expected to be officially delivered by the end of 2025

2026-2027 Technology Roadmap:

• The Xuantie processor family plans include C908X (the first AI-specific processor supporting 4096 bits RVV extension), R908A (for automotive applications), and XL200 (providing larger-scale multi-cluster coherent interconnect)

• Meta’s second-generation AI chip will adopt the RISC-V core from Andes Technology, planned for mass production in 2026, featuring a 15-stage out-of-order superscalar pipeline and supporting multi-core expansion capabilities with the CHI protocol

• By the end of 2026, the performance gap between high-end ARM and RISC-V CPU cores is expected to narrow to nearly parity

2027-2030 Technology Roadmap:

• The RVA30 roadmap has been initiated, which will be the next generation standard following RVA23

• By 2030, RISC-V’s market share in the global semiconductor market is expected to exceed 25%

• In the data center field, heterogeneous computing-based hybrid accelerators will dominate

3.3 Directions and Breakthroughs in Technological Innovation

Technological innovations in RISC-V AI chips are breaking through in multiple directions:

Matrix Extension Standardization: The RISC-V community is exploring four matrix extension solutions: Zvdot (batch dot product), VME (vector-matrix), AME (independent matrix engine), transitioning from “matrix in vector” to “separate matrix,” ultimately achieving standardization through fast-track proposals.

Evolution of Vector Extensions: RVV (RISC-V Vector Extension) v1.0 has become a foundational pillar supporting AI computing, supporting mixed precision operations of various data types, scalable vector lengths (up to 16Kb per register), and width expansion and compression operations.

Improvement of Software Ecosystem: NVIDIA has announced that it is bringing CUDA platform support to the RISC-V instruction set architecture, aiming to achieve compatibility between RISC-V and the CUDA ecosystem. This will significantly enhance RISC-V’s competitiveness in the AI software ecosystem.

Packaging Technology Innovations: Advanced packaging technologies such as 3D stacking and silicon photonic interconnects are being applied in RISC-V AI chip designs to break through traditional packaging’s bandwidth and power consumption limitations.

Dedicated Instruction Set Extensions: Various manufacturers are developing dedicated AI instruction set extensions, such as Xuantie’s Matrix instructions and SiFive’s Intelligence extensions, to provide higher AI computing efficiency.

4. In-Depth Comparison of Key Technical Dimensions

4.1 Comparison of Memory Architecture Technologies

The choice of memory architecture directly affects the performance of AI chips. The following is a comparative analysis of different memory architectures from multiple dimensions:

Technical Dimension	HBM Architecture	DDR Architecture	Hybrid Architecture	Compute-Storage Integrated Architecture
Bandwidth Level	300-3200GB/s	70-1000GB/s	200-768GB/s	Extremely High (Eliminates Transport)
Latency Characteristics	50-100ns	10-20ns	Medium	Extremely Low
Power Consumption Performance	High (Requires Cooling)	Medium	Low	Extremely Low
Cost Level	Extremely High	Medium	Medium	Low (Same Process)
Capacity Support	16-64GB	32-2048GB	64-768GB	Limited by On-Chip Storage
Technology Maturity	High (Mass-Produced)	Extremely High	Medium	Low (Prototype Stage)
Applicable Scenarios	Cloud Large Model Training	General Computing	Edge AI	Dedicated Inference

Advantages of HBM Architecture: HBM achieves extremely high bandwidth density through 3D stacking technology, with HBM3e reaching a bandwidth of 3.2TB/s, over 30 times that of DDR5. This makes it particularly suitable for training tasks of large-scale AI models. However, HBM is costly, has high power consumption, and requires complex cooling designs.

Advantages of DDR Architecture: DDR memory technology is mature, relatively low-cost, and has strong capacity scalability. DDR5 has significant improvements in bandwidth and energy efficiency compared to DDR4, with single-channel bandwidth reaching 70-100GB/s. DDR architecture is suitable for cost-sensitive scenarios with high memory capacity requirements.

Innovations in Hybrid Architecture: Some manufacturers are exploring hybrid designs of LPDDR and DDR, such as Qualcomm’s AI200/AI250 using LPDDR memory to provide 768GB capacity, meeting large capacity needs while reducing power consumption.

Breakthroughs in Compute-Storage Integrated Architecture: Compute-storage integrated architecture fundamentally eliminates data transport overhead by merging computing units with storage units. Micronano Core’s 3D-CIM technology achieves a 4-fold increase in computing power density and a 5-10 times improvement in energy efficiency at the same process.

4.2 Analysis of AI Acceleration Unit Architectures

The AI acceleration unit is the core competitiveness of RISC-V AI chips. The following is a detailed analysis of different architectures:

Vector Processor Architecture: The SiFive Intelligence series adopts a vector processor architecture, with X280 Gen 2 equipped with a 512-bit vector length, closely integrated with SiFive Intelligence extension instructions and an 8-stage dual-issue in-order scalar pipeline. The advantage of this architecture lies in its high flexibility, allowing optimization of various AI operators through vector instructions, but it is relatively inefficient in matrix-intensive scenarios.

Tensor Core Architecture: Hanguang 800 adopts a self-developed neural network processor (NPU) architecture, integrating 192M local storage (SRAM), achieving high computing power and low latency through proprietary computing engines and execution units. This architecture is specifically optimized for deep learning models such as CNNs, performing excellently in inference tasks.

Pulsed Array Architecture: Some prototype designs adopt pulsed array architectures, such as the deep convolution engine (DWE) of the DARKSIDE system, which uses a pulsed array design to achieve a performance of 30 MAC/cycle, over 10 times faster than the software execution of 8 RVNN cores. The advantage of pulsed arrays lies in their high data reuse rate, making them suitable for compute-intensive operations like matrix multiplication.

Hybrid Architecture Design: Tenstorrent’s Tensix AI core adopts a hybrid architecture, containing tiled math engines and vector math engines, with the former supporting Int8, TF32, BF/FP16, FP8, and 2-bit to 8-bit floating-point data types, while the latter mainly targets FP32, INT16, and INT32 data types. This design provides better flexibility and performance balance.

4.3 Performance-Power Ratio and Energy Efficiency Evaluation

Energy efficiency ratio is a key indicator of the competitiveness of AI chips. The following is a comparison of the energy efficiency performance of different RISC-V AI chips:

Chip Product	Process Node	Computing Performance	Energy Efficiency Ratio	Power Consumption Level	Characteristics
Hanguang 800	12nm	825 TOPS (INT8)	500 IPS/W	276W	Cloud Inference Optimization
DARKSIDE	65nm	65 GOPS (INT2)	835 GOPS/W	156mW	Ultra-Low Power Edge
Xuantie C930	12nm	8 TOPS Matrix	–	–	General + AI Fusion
Jintide Shikong K1	12nm	2 TOPS	–	–	Edge AI Optimization
Micronano Core 3D-CIM	To Be Announced	–	5-10 Times Improvement	Significantly Reduced	Compute-Storage Integrated Architecture

Energy Efficiency Ratio Analysis: The data shows that chips for different application scenarios exhibit significant differences in energy efficiency ratios. The DARKSIDE system achieved an energy efficiency ratio of 835 GOPS/W under a 65nm process, mainly due to its specialized design for ultra-low power edge applications. Hanguang 800 achieved an energy efficiency ratio of 500 IPS/W under a 12nm process, performing excellently in cloud inference scenarios.

Power Consumption Optimization Strategies: Various manufacturers have adopted multiple power consumption optimization technologies:

• Dynamic Voltage Frequency Scaling (DVFS): Adjusting voltage and frequency in real-time based on workload

• Clock Gating Technology: Turning off clocks in unused modules to reduce power consumption

• Process Technology Optimization: Using more advanced process technologies to reduce leakage power consumption

• Architecture Optimization: Reducing data transport power consumption through new architectures like compute-storage integration

Performance Density Comparison: Micronano Core’s 3D-CIM technology achieves a 4-fold increase in computing power density through compute-storage integrated architecture at the same process. This indicates that architectural innovation has great potential in enhancing performance density.

4.4 Comparison of Software Ecosystem and Development Toolchains

The level of completeness of the software ecosystem directly affects the market competitiveness and user acceptance of RISC-V AI chips:

Compiler Support:

• Alibaba T-Head’s self-developed “Xuantie Compiler” supports RISC-V architecture chips and is compatible with TensorFlow/PyTorch

• SiFive provides an MLIR-based compiler toolchain that supports XNNPACK accelerated inference

• Tenstorrent has developed toolchains such as TT-MLIR and TT-Forge, supporting various AI frameworks

Framework Compatibility:

Most RISC-V AI chips are striving to achieve compatibility with mainstream AI frameworks:

• TensorFlow Support: Almost all manufacturers claim to support TensorFlow

• PyTorch Support: Achieved through ONNX conversion or native support

• ONNX Support: Widely supported as an intermediate format for model conversion

• Dedicated Frameworks: Some manufacturers have developed their own AI frameworks, such as Huawei’s MindSpore

Development Tool Comparison:

Manufacturer	Development Toolchain	Features	Maturity
Alibaba T-Head	Xuantie Compiler, Wujian Platform	Full-stack support, complete ecosystem	High
SiFive	MLIR Toolchain, XNNPACK	High standardization	High
Tenstorrent	TT-Metalium, TT-NN	CUDA-like programming model	Medium
Huawei HiSilicon	CANN, MindSpore	Deep optimization, self-developed ecosystem	High

Current Status of Ecosystem Development:

The RISC-V AI ecosystem is rapidly developing, but there is still a gap compared to the mature x86 and ARM ecosystems. Major challenges include:

• The maturity of the software toolchain needs to be improved

• Lack of unified programming standards

• Limited support for third-party libraries and frameworks

• Insufficient talent cultivation and technical accumulation

However, with NVIDIA announcing support for the CUDA platform and continuous investment from major manufacturers, the RISC-V AI ecosystem is expected to achieve significant breakthroughs in the next 2-3 years.

5. Technical Selection Recommendations in Data Center Scenarios

5.1 Scenario Demand Matching Analysis

Based on different application scenarios in data centers, the selection of RISC-V AI chips needs to consider the following factors:

AI Training Scenario Demand Analysis:

AI training scenarios have extremely high requirements for computing power, memory bandwidth, and scalability. Typical requirements include:

• Computing Power Requirement: Typically requires computing power from hundreds of TFLOPS to several PFLOPS

• Memory Requirement: Needs to support TB-level parameter storage, with bandwidth requirements exceeding 1TB/s

• Scalability: Needs to support large-scale clusters, such as tens of thousands of cards

• Precision Support: Needs to support high-precision computing such as FP32, BF16

Suitable RISC-V AI chips include: Huawei Ascend 910C (352 TOPS, supports 160,000 card clusters), MuXi Cloud C500 (300 TOPS, 3.35TB/s bandwidth), etc.

AI Inference Scenario Demand Analysis:

AI inference scenarios focus more on energy efficiency ratios and latency control. Typical requirements include:

• Energy Efficiency Optimization: Needs to reduce power consumption while ensuring performance

• Low Latency: Inference latency is typically required to be in the millisecond range

• Flexible Deployment: Supports various model and precision configurations

• Cost Control: Controls hardware costs while meeting performance requirements

Suitable RISC-V AI chips include: Hanguang 800 (825 TOPS INT8, 500 IPS/W energy efficiency ratio), Xuantie C930 (8 TOPS Matrix, general + AI fusion), etc.

Edge Data Center Demand Analysis:

Edge data centers have special requirements for power consumption, cost, and reliability:

• Low Power Consumption: Typically requires total machine power consumption at the hundred-watt level

• High Reliability: Needs to operate stably 24/7

• Cost Sensitivity: Strict control over hardware costs

• Environmental Adaptability: Needs to adapt to various environmental conditions

Suitable RISC-V AI chips include: Jintide Shikong K1 (2 TOPS, edge AI optimization), DARKSIDE (835 GOPS/W energy efficiency ratio), etc.

5.2 Comprehensive Cost-Benefit Assessment

When making technical selections, cost-effectiveness is a key consideration. The following is a cost-benefit analysis of RISC-V AI chips from multiple dimensions:

Hardware Cost Comparison:

According to market information, there are significant cost differences among different RISC-V AI chips:

• High-End Products (e.g., Huawei Ascend 910C, MuXi C500): Higher costs, mainly aimed at large data centers

• Mid-Range Products (e.g., Xuantie C930, SiFive X280): Moderate costs, suitable for small and medium-sized enterprise data centers

• Edge Products (e.g., Jintide Shikong K1): Lower costs, suitable for edge computing scenarios

Energy Efficiency Cost Analysis:

The energy efficiency ratio directly affects the operating costs of data centers. For a typical 1MW data center:

• Using high-energy efficiency chips (800 GOPS/W): Can support about 800 TOPS of computing power

• Using ordinary chips (200 GOPS/W): Only supports about 200 TOPS of computing power

• Annual Electricity Cost Difference: Assuming an electricity price of 0.8 yuan/kWh, running for 8,760 hours a year, the annual electricity cost for 1MW power is about 7 million yuan

Total Cost of Ownership (TCO) Assessment:

TCO should include hardware procurement costs, deployment costs, operation and maintenance costs, and energy costs:

• Initial Investment: Includes costs for chips, servers, network devices, etc.

• Deployment Costs: Includes system integration, software deployment, personnel training, etc.

• Operation and Maintenance Costs: Includes daily maintenance, upgrades, fault handling, etc.

• Energy Costs: The cost of electricity consumption in data centers

Return on Investment Analysis:

Based on current market data, the return on investment for RISC-V AI chips is mainly reflected in:

• Cost Advantage: Compared to x86 and ARM architectures, RISC-V has the advantage of no licensing fees

• Performance Improvement: Achieving higher performance density through architectural innovation

• Customization Capability: Hardware can be customized according to needs, improving efficiency

• Ecological Development: As the ecosystem improves, software costs will gradually decrease

5.3 Supply Chain Risk and Technical Support Assessment

When making technical selections, the stability of the supply chain and the ability to provide technical support are essential factors to consider:

Supply Chain Risk Assessment:

• Wafer Foundry: Mainly relies on foundries such as TSMC and SMIC, requiring assessment of capacity and geopolitical risks

• Packaging and Testing: The capacity and technical capabilities of advanced packaging (e.g., HBM, 3D stacking)

• Key IP: The stability of supply for key IPs such as DDR controllers, PCIe interfaces, etc.

• Raw Materials: Supply risks for key materials such as photoresist, target materials, etc.

Technical Support Capability Assessment:

Manufacturer	Technical Support Capability	Service Coverage	Response Speed	Technical Strength
Alibaba T-Head	Strong (Self-Developed Full Stack)	Global	Fast	High
Huawei HiSilicon	Strong (Full Industry Chain)	Mainly in China	Fast	Very High
SiFive	Medium (IP Licensing Model)	Global	Medium	High
Startups	Weak (Limited Resources)	Regional	Slow	Medium

Ecological Support Assessment:

• Software Ecosystem: The level of completeness of compiler, toolchain, and framework support

• Community Support: The activity level and technical contributions of the open-source community

• Talent Reserve: The market supply situation of relevant technical talents

• Standardization Level: The unification and interoperability of technical standards

Risk Mitigation Strategies:

To reduce supply chain risks, the following strategies are recommended:

1. Diversified Supplier Strategy: Choose multiple suppliers to spread risks

1. Technical Reserve: Establish independent technical capabilities to reduce external dependencies

1. Long-Term Cooperation: Establish long-term strategic partnerships with key suppliers

1. Localization Strategy: Prioritize suppliers with local production capabilities

6. Technology Development Trends and Outlook

6.1 Recent Development Focus (2025-2026)

RISC-V AI chips will enter a critical development period in 2025-2026, with the main development focuses including:

Establishment of Technical Standards:

• The RVA30 standard has been initiated: The new generation standard roadmap following RVA23 has been opened

• Matrix extension standardization: Matrix extension solutions such as Zvdot, VME, AME will achieve standardization through fast-track proposals

• Compute-storage integration standards: The world’s first RISC-V compute-storage integration standard development work has been initiated

Acceleration of Product Mass Production:

• SiFive’s second-generation Intelligence series products will begin shipping in Q2 2026

• Jintide Shikong’s third-generation RISC-V AI CPU chip is expected to enter mass production by the end of 2026

• Several startups’ first products will enter the mass production stage

Breakthroughs in Ecosystem Construction:

• NVIDIA CUDA platform support: NVIDIA is bringing CUDA platform support to the RISC-V architecture

• Mainstream framework adaptation: Native support for frameworks like TensorFlow and PyTorch will gradually improve for RISC-V

• Development tools maturity: The stability and functionality of compilers, debuggers, and other development tools will significantly improve

Performance Improvement Expectations:

• General Performance: The performance gap between high-end RISC-V CPUs and ARM cores will narrow to near parity

• AI Performance: AI computing power will increase by 2-4 times through vector and matrix extensions

• Energy Efficiency Optimization: Energy efficiency ratios will improve by 50-100% through architectural innovations and process improvements

6.2 Medium to Long-Term Technology Evolution Path (2026-2027)

In 2026-2027, RISC-V AI chips will achieve significant breakthroughs in multiple technical dimensions:

Architectural Innovation Directions:

• Compute-storage integration technology maturity: 3D-CIM and other compute-storage integrated architectures will transition from prototypes to mass production, achieving a 4-fold increase in computing power density

• Ultra-heterogeneous computing: The multi-engine fusion architecture of CPU+GPU+NPU+DPU will become mainstream

• Near-data computing: The deep integration of computing units and storage units will significantly reduce data transport

Process Technology Evolution:

• Widespread adoption of advanced processes: Mainstream products will adopt 7nm and below advanced processes

• Specialized process applications: Dedicated process platforms optimized for AI computing will emerge

• Heterogeneous integration: Chiplets of different process nodes will be integrated through advanced packaging technologies

Interconnect Technology Breakthroughs:

• High-speed interconnect: Interconnect bandwidth between chiplets will reach over 100GB/s

• Silicon photonic interconnect: Optical communication technology will be introduced into chip interconnects

• Standardized interfaces: Standardized interconnect interfaces like UCIe will be widely used

Application Scenario Expansion:

• Data center penetration: The penetration rate of RISC-V AI chips in data centers will increase from currently less than 5% to over 20%

• Edge computing explosion: Applications in edge AI scenarios will experience explosive growth

• Breakthroughs in dedicated fields: Achieving large-scale applications in vertical fields such as autonomous driving and smart manufacturing

6.3 Industry Ecosystem Maturity Forecast

The maturity of the RISC-V AI chip industry ecosystem will achieve leapfrog development in the coming years:

Market Size Forecast:

According to industry forecast data, the RISC-V chip market will show rapid growth:

• 2025: Global market share of 12%, mainly applied in embedded systems

• 2026: Market share of 18%, beginning to enter the consumer market

• 2027: Market share of 25%, expanding enterprise-level applications, competing with ARM

• 2028: Market share of 32%, penetrating the high-end market

• 2030: Market share of 40%, becoming one of the mainstream architectures

Technology Maturity Assessment:

• 2025: Basic technology matures, products begin large-scale deployment

• 2026: Key technological breakthroughs, performance approaching mainstream architectures

• 2027: Ecosystem basically complete, ready for large-scale commercial conditions

• 2028: Technological leadership emerges, beginning to lead innovation directions

Indicators of Ecosystem Completeness:

• Software Toolchain: From current basic functionality to comprehensive functional support

• Framework Compatibility: From supporting through conversion to native efficient support

• Talent Cultivation: From a few experts mastering to a large-scale talent supply

• Standardization: From following standards to leading standardization

Key Success Factors:

1. Performance Catch-Up: General performance reaches or approaches ARM/x86 levels

1. Ecological Construction: Establish a complete software toolchain and development ecosystem

1. Application Traction: Achieve large-scale applications in key application scenarios

1. Standardization Promotion: Promote the formulation and unification of key technical standards

1. Investment Support: Continuous R&D investment and industrial policy support

Potential Challenges and Responses:

Despite the broad prospects, RISC-V AI chips still face many challenges:

• Performance Gap: There are still gaps with mature architectures in certain scenarios, requiring architectural innovation to bridge

• Ecological Fragmentation: Different manufacturers’ extended instruction sets are not unified, requiring strengthening of standardization

• Talent Shortage: There is a shortage of relevant technical talents, necessitating strengthening of the training system

• Market Awareness: User acceptance of new technologies requires time to establish

• Supply Chain Risks: The supply security of key technologies and equipment needs to be guaranteed

Through continuous technological innovation, ecosystem construction, and market cultivation, RISC-V AI chips are expected to achieve a market landscape of tripartite competition with ARM and x86 by 2027-2028, providing more open, flexible, and efficient solutions for AI computing in data centers.