Source: Content from IP and SOC design, thank you!
@Mark:
The biggest change in the past decade is low power design. Ten years ago, low power design mainly focused on reducing dynamic power, employing various clock gating techniques, and preventing unused modules from toggling.
In the last ten years, static power leakage has become a major power consumer. Therefore, in addition to various methods for saving dynamic power, power gating has increasingly become the mainstream method for lower power management.
In the early days, power gating was often done manually, inserting clamping and level shifters into the netlist using scripts.
In the past 5-6 years, the flow of CPF/UPF has matured significantly, and most of these manual tasks are now handled by EDA tools. Furthermore, UPF can now be directly annotated to RTL for front-end simulation, greatly reducing the workload for lower power design.
Source: https://www.zhihu.com/people/ma-ke-97-59
@Wang Kellen:
I have maintained ASIC code from 1997, and I’d like to share some points that have been particularly impacted.
In the early days, circuit design was very extreme and exhibited a minimalist approach. For example:
1. Large-scale use of latches instead of registers in chips to save area.
2. Extensive use of pseudo-random number generators in combinational circuits instead of adders or subtractors, such as in typical counter circuits, since we only care about the counting cycle and underflow judgment. The counter counting from 1 to 16 is irrelevant, leading to the use of pseudo-random number generators to count, as long as the numbers do not repeat and we count to 0 for underflow. The circuit only requires N registers and an XOR gate, which is much simpler than an adder, though it is more cumbersome to use as you need to look up the initial values in a table.
3. The most intolerable aspect was the very small scale of early circuits, leading to extreme address space compression. At that time, the system’s address documentation separated read and write functionalities, and the meanings of most addresses for reading and writing were completely different. This means that address utilization was nearly maximized; every address was used. An address for a read-only register could also be written to, but the write functionality was assigned to another write-only register. Generally, the read-write characteristics of each function were highly compressed; if a function only needed to be written to be effective, it was definitely not readable. There were rarely functions that could be written and read simultaneously. At that time, software could not write a value to a register address and read it back to confirm correctness, because if every register could be read and written, there wouldn’t be enough addresses! The division of address ranges was also particularly fine-grained, with assigned address spaces for certain modules being nearly fully utilized.
4. Before hardware description languages appeared, circuits were built with gates, so many long-standing products underwent the process of translating circuits into hardware description languages (some even initially fell into the VHDL trap and had to translate again when Verilog appeared). At that time, automatic synthesis tools were still new and relatively weak in functionality, relying mainly on engineers’ accurate grasp of circuits and timing to ensure the consistency between code and synthesis results. However, engineers during this period had a much deeper understanding of circuits, so unconventional circuits were often designed using strange expressions.
Source: https://www.zhihu.com/people/KellenWang
@CleverPlus:
I have been thinking about the direction of process technology after 3nm. Is it a change of substrate? Or will it continue to advance?
I tend to believe that silicon will stop at 2nm. Even 2nm has been delayed for a long time (with 3nm remaining for quite a while).
So what is the impact on today’s SOCs?
With the slowdown of process technology, we can only work harder on design. Whether it is introducing NPU or early ISPs, SOCs are increasingly integrating ASICs. Even CPUs and GPUs can be understood as ASICs.
In the future, SOCs will incorporate more ASICs.
Of course, ASICs from ten years ago are somewhat different from today. Today’s ASICs not only pursue customization and semi-customization but are also evolving towards variable customization, namely FPGAs, which is Intel’s focus. There are influential figures on Bilibili explaining this, which you can check out.
Essentially, it combines the efficiency of ASICs with the versatility of general-purpose processors.
However, FPGAs are challenging to work with, and some even consider it a wrong direction (with fatal flaws).
But in SOCs, there will be more collections of ASICs; this direction is not only certain but also underway, especially with the slowdown in process technology advancement. NPUs are obvious examples of ASIC characteristics. In the future, there will be more functionalities segmented to create ASICs; we will wait and see. After all, traditional computing with CPUs and GPUs is becoming increasingly unviable.
This is the difference between ten years ago and now.
Source: https://www.zhihu.com/people/ye-lai-liao-669