Computer Science
Assembly Optimization of an AES-128-CTR Algorithm Based on a Cortex-M4 Core
Dongxuan YANG1, Ganggang ZHANG2, Xinliang LIU1
1. School of E-commerce and Logistics, Beijing Technology and Business University; 2. Digital Campus, Capital Normal University
Abstract:
With the rapid development of the Internet of Things, embedded hardware products face great challenges in data security. The AES (Advanced Encryption Standard) algorithm has the advantages of strong attack resistance, fast operation speed, and flexible block length in the field of data encryption and decryption. The speed of this algorithm on microcontroller platforms is far inferior to general-purpose CPUs (Central Processing Units) which have an extended instruction set for AES encryption. To solve this problem, a speed optimized AES algorithm in CTR (Counter) mode based on the Cortex-M4 core instruction set is implemented using assembly language. The kernel’s unique barrel shifter and three-stage pipeline are used to optimize the round transformation of the algorithm, and the number of instruction cycles is reduced. Testing on an FRDM-K82F development board shows that the assembly optimization of the algorithm is substantially more efficient than the code implemented using the C language, and it offers more advantages in both cost and power consumption compared to hardware encryption based on the coprocessor.
Keywords:
assembly optimization, AES, Cortex-M4
Corresponding Author:
Ganggang ZHANG, Engineer at the School of E-commerce and Logistics, Beijing Technology and Business University, research direction in educational informatization.
Funding Support:
National Key Research and Development Program Subproject (2016YFD0401205); Beijing Natural Science Foundation (4202014); Beijing Municipal Science and Technology Commission Project (Z191100008619007)
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