It is well known that RISC-V processor IPs are significantly cheaper than ARM. If your management asks you to consider domestic IP alternatives or budget reductions, the domestic RISC-V IP is undoubtedly the first choice. When comparing performance, should ARM’s NEON be compared to RISC-V’s P extension or V extension? First, let’s introduce RISC-V’s P and V extensions. P stands for DSP extension, which is a scalar SIMD instruction extension; V stands for Vector, which is the vector extension. The two key differences are that the P extension does not add new general-purpose registers, and the data length is fixed, with the maximum supported data length being the same as that of ordinary general-purpose registers, typically 32 or 64 bits; the V extension adds a set of vector general-purpose registers, with variable data length, generally starting from 128 bits, providing greater computational power. Different IP vendors implement the P extension in various ways. As far as I know, some reuse integer execution units, while others directly use the V extension to implement the P extension, such as the Xuantie series (E908/E920) from T-head. So, what is ARM’s NEON like? We often refer to it as a set of SIMD extensions, which, on the surface, seems to correspond to RISC-V’s P extension. However, if we look at the instruction set and the V8 architecture, we will find that it includes 16/32 128-bit vector registers and supports both integer and floating-point operations. From this perspective, it aligns more with the V extension. Some may ask, since NEON reuses integer execution units and does not have new vector execution units, shouldn’t it correspond to the P extension? This is from a hardware perspective, which is an architectural comparison, but from a software perspective, the V extension is more similar.
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NEON Programming Model: Programmers see128-bit vector registers (Q0-Q15, D0-D31) and a complete set of instructions for operating on these vectors (addition, multiplication, loading, storing, etc.). The programmer’s mindset is: “I have this packaged data, and I want to operate on the entire vector with a single instruction.”
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RISC-V V Extension Programming Model: Programmers seevariable-length vector registers (v0-v31) and a complete set of more powerful vector instructions. The programmer’s mindset is also: “I have these variable-length vectors, and I want to operate on the entire vector with a single instruction.”
When evaluating performance, for rigor, if the product line/client proposes a requirement to benchmark against ARM’s NEON processors, we need to confirm whether the evaluated RISC-V IP supports the V extension. If it does not support it, we need to confirm whether the performance of processors supporting the P extension is sufficient, which is closely related to the specific application. If it is sufficient, there is no need to insist on using a processor with the V extension, as once the V extension is configured, it will have a whole new vector pipeline, significantly increasing the area.