Application and Practice of Voltage Dip Testing in Siemens PLC Systems

Voltage dip testing is a key step in evaluating the anti-interference capability of industrial equipment. Proper implementation can effectively improve system stability and avoid production losses.

1. System Debugging Methods

Step-by-Step Debugging Method

The voltage dip testing debugging should adopt a progressive method to ensure that each part of the system performs stably under abnormal voltage conditions. First, basic functionality verification should be conducted to confirm that the system operates normally under normal voltage; then, small-scale dip tests should be performed, gradually increasing the test intensity.

// Debug mode selection function block

FUNCTION_BLOCK "FB_TestModeSelect"

{ S7_Optimized_Access := 'TRUE' }

VERSION : 0.1

   VAR_INPUT 

      TestMode : Int;    // 1-Basic test, 2-Small dip, 3-Medium dip, 4-Large dip

      StartTest : Bool;  // Test start signal

   END_VAR

   VAR_OUTPUT 

      TestActive : Bool;     // Test activation status

      TestCompleted : Bool;  // Test completion signal

   END_VAR

   VAR 

      TestState : Int := 0;  // Test state: 0-Standby, 1-Preparation, 2-Execution, 3-Recovery, 4-Completion

   END_VAR


BEGIN

   // Test mode selection logic

   CASE TestState OF

      0:  // Standby state

         IF StartTest THEN

            TestState := 1;

            TestActive := TRUE;

            TestCompleted := FALSE;

         END_IF;

      1:  // Preparation state - Actions can be added here before the test

         TestState := 2;

      2:  // Execution state - Actual voltage dip test execution

         // Implement interaction with hardware here to trigger actual voltage dip

         // ...

         TestState := 3;

      3:  // Recovery state

         // Wait for the system to recover to normal

         // ...

         TestState := 4;

      4:  // Completion state

         TestActive := FALSE;

         TestCompleted := TRUE;

         TestState := 0;

   END_CASE;

END_FUNCTION_BLOCK

Parameter Tuning Steps

Parameter tuning for voltage dip testing is crucial to ensure the effectiveness of the test. The test voltage amplitude, duration, and dip frequency need to be set according to the characteristics of the tested equipment and relevant standards. A typical parameter tuning process includes:

1. Determining the allowable dip range based on equipment specifications

2. Setting test levels according to standards (e.g., IEC 61000-4-11)

3. Establishing a test parameter data block

// Voltage dip test parameter data block

DATA_BLOCK "DB_VoltDipParams"

{ S7_Optimized_Access := 'TRUE' }

VERSION : 0.1

NON_RETAIN

   STRUCT 

      DipLevel : Array[1..4] of Real;    // Dip amplitude levels (%)

      DipDuration : Array[1..4] of Time; // Dip duration

      RecoveryTime : Array[1..4] of Time;// Recovery wait time

      RepeatCount : Array[1..4] of Int;  // Number of repeat tests

      CurrentLevel : Int := 1;           // Current test level

      CurrentConfig : Struct             // Current configuration used

         Level : Real;

         Duration : Time;

         Recovery : Time;

         Repeats : Int;

      END_STRUCT;

   END_STRUCT;

BEGIN

   DipLevel[1] := 30.0;    // 30% dip (drops to 70% rated voltage)

   DipLevel[2] := 50.0;    // 50% dip

   DipLevel[3] := 70.0;    // 70% dip

   DipLevel[4] := 90.0;    // 90% dip (almost complete power outage)

   
   DipDuration[1] := T#200MS;  // 200 milliseconds

   DipDuration[2] := T#500MS;  // 500 milliseconds

   DipDuration[3] := T#1S;     // 1 second

   DipDuration[4] := T#5S;     // 5 seconds

   
   RecoveryTime[1] := T#5S;    // Recovery wait time

   RecoveryTime[2] := T#10S;

   RecoveryTime[3] := T#20S;

   RecoveryTime[4] := T#30S;

   
   RepeatCount[1] := 3;        // Number of repeat tests

   RepeatCount[2] := 3;

   RepeatCount[3] := 2;

   RepeatCount[4] := 1;        // Severe dips should be tested less

END_DATA_BLOCK

Abnormal Simulation Testing

Abnormal simulation is the core of voltage dip testing. In Siemens PLC systems, abnormal simulation can be achieved in the following ways:

1. Using dedicated voltage dip generator hardware

2. Controlling relays to switch load power through PLC

3. Program simulation response verification (suitable for software response testing)

// Abnormal simulation control function block

FUNCTION_BLOCK "FB_DipSimulation"

{ S7_Optimized_Access := 'TRUE' }

VERSION : 0.1

   VAR_INPUT 

      Execute : Bool;             // Execution trigger signal

      DipLevel : Real;            // Dip amplitude (%)

      DipDuration : Time;         // Dip duration

      EnableHardwareControl : Bool; // Enable hardware control

   END_VAR

   VAR_OUTPUT 

      Busy : Bool;                // In progress

      Done : Bool;                // Execution completed

      Error : Bool;               // Error flag

      StatusCode : Word;          // Status code

   END_VAR

   VAR 

      State : Int := 0;           // Internal state machine

      StartTime : Time;           // Start time

      DipControl : Bool;          // Dip control signal

   END_VAR


BEGIN

   CASE State OF

      0:  // Standby state

         IF Execute THEN

            Busy := TRUE;

            Done := FALSE;

            Error := FALSE;

            StatusCode := W#16#0000;

            StartTime := RUNTIME(1);

            State := 1;

         END_IF;

      1:  // Preparation state

         // Safety checks can be added here

         IF EnableHardwareControl THEN

            // Hardware control mode

            DipControl := TRUE;  // Activate external hardware

            // Assume DipControl connects to output points, controlling external power switching devices

            State := 2;

         ELSE

            // Software simulation mode

            State := 10;  // Jump to software simulation state

         END_IF;

      2:  // Hardware control - dip activation

         IF RUNTIME(1) - StartTime >= DipDuration THEN

            DipControl := FALSE;  // End dip

            State := 3;

         END_IF;

      3:  // Hardware control - completion

         Busy := FALSE;

         Done := TRUE;

         State := 0;

      10: // Software simulation state

         // Simulate system response to voltage dip here

         // ...

         State := 11;

      11: // Software simulation completed

         Busy := FALSE;

         Done := TRUE;

         State := 0;

   END_CASE;
   
   // Output control to actual hardware (e.g., connected to Q address)
   // For example: %Q0.0 := DipControl;
END_FUNCTION_BLOCK

Performance Verification Key Points

Performance verification after voltage dip testing is a key step in confirming the system’s anti-interference capability. Verification content includes:

1. Whether the system recovers normally after the dip

2. Whether data integrity is maintained

3. Whether communication functions are normal

4. Whether key control functions are affected

Performance verification should establish clear pass/fail criteria and use dedicated function blocks to record test results:

// Performance verification function block

FUNCTION_BLOCK "FB_PerformanceVerification"

{ S7_Optimized_Access := 'TRUE' }

VERSION : 0.1

   VAR_INPUT 

      StartVerification : Bool;   // Start verification

      ResetResults : Bool;        // Reset results

   END_VAR

   VAR_OUTPUT 

      VerificationDone : Bool;    // Verification completed

      SystemRecovered : Bool;     // System has recovered

      DataIntegrityOK : Bool;     // Data integrity normal

      CommunicationOK : Bool;     // Communication function normal

      ControlFunctionOK : Bool;   // Control function normal

      OverallResult : Bool;       // Overall result

   END_VAR

   VAR 

      VerState : Int := 0;        // Verification state

   END_VAR


BEGIN

   // Reset results

   IF ResetResults THEN

      VerificationDone := FALSE;

      SystemRecovered := FALSE;

      DataIntegrityOK := FALSE;

      CommunicationOK := FALSE;

      ControlFunctionOK := FALSE;

      OverallResult := FALSE;

      VerState := 0;

   END_IF;
   
   // Verification state machine

   CASE VerState OF

      0:  // Standby state

         IF StartVerification THEN

            VerState := 1;

         END_IF;
         
      1:  // System recovery verification

         // Check CPU status, key inputs/outputs, system flags, etc.

         // ...

         SystemRecovered := TRUE;  // Set based on actual check results

         VerState := 2;

      2:  // Data integrity verification

         // Check key data blocks, parameters, persistent data, etc.

         // ...

         DataIntegrityOK := TRUE;  // Set based on actual check results

         VerState := 3;

      3:  // Communication function verification

         // Verify various communication interfaces

         // ...

         CommunicationOK := TRUE;  // Set based on actual check results

         VerState := 4;

      4:  // Control function verification

         // Test key control logic

         // ...

         ControlFunctionOK := TRUE;  // Set based on actual check results

         VerState := 5;

      5:  // Summarize results

         OverallResult := SystemRecovered AND DataIntegrityOK AND 

                         CommunicationOK AND ControlFunctionOK;

         VerificationDone := TRUE;

         VerState := 0;

   END_CASE;

END_FUNCTION_BLOCK

2. Fault Diagnosis and Troubleshooting

Common Fault Analysis

Common faults in voltage dip testing mainly include:

1. The system cannot recover from the dip: Usually caused by insufficient system power design or improper design of the hold circuit

2. Data loss or errors: May be due to improper settings of data block persistence or lack of backup mechanisms

3. Communication interruption: Network devices or communication modules are highly sensitive to voltage dips

4. Control logic anomalies: The program lacks appropriate exception handling mechanisms

Use of Diagnostic Tools

Siemens PLC provides various diagnostic tools to help analyze the system status after voltage dips:

1. TIA Portal Diagnostic Buffer: Records system events and errors

2. SIMATIC ProDiag: Advanced tool for process diagnostics

3. System Status Monitoring: View CPU status through system data blocks

4. Communication Diagnostics: Network interface and bus system diagnostic functions

Troubleshooting Methodology

Troubleshooting after voltage dip testing should follow a systematic approach:

1. Collect information: Record dip parameters, fault phenomena, and diagnostic buffer contents

2. Locate the problem area: Determine whether it is a hardware fault, communication fault, or program logic issue

3. Root cause analysis: Identify direct and root causes

4. Develop solutions: System improvements based on root causes

Case Analysis

A food production line experienced a loss of recipe parameters after voltage dip testing, affecting product quality control. Analysis revealed:

1. Problem description: After the voltage dip, the recipe parameters displayed on the HMI reset to default values

2. Root cause analysis: The recipe data block was not set to be persistent, and there was a lack of UPS protection

3. Solution:

// Improved recipe data block definition

DATA_BLOCK "DB_RecipeParams"

{ S7_Optimized_Access := 'TRUE' }

VERSION : 0.1

RETAIN  // Add RETAIN attribute to ensure persistence during power loss

   STRUCT 

      RecipeID : Int;

      RecipeName : String[30];

      Parameters : Array[1..20] of Real;

      LastModified : Date_And_Time;

      CheckSum : DWord;  // Add checksum for data integrity verification

   END_STRUCT;

BEGIN

   RecipeID := 1;

   RecipeName := 'Default Recipe';

   // Initialize parameters and checksum

END_DATA_BLOCK


// Recipe data integrity verification function block

FUNCTION "FC_VerifyRecipeIntegrity" : Bool

{ S7_Optimized_Access := 'TRUE' }

VERSION : 0.1

   VAR_IN_OUT 

      RecipeDB : "DB_RecipeParams";

   END_VAR

   VAR_TEMP 

      CalcChecksum : DWord;

   END_VAR


BEGIN

   // Calculate checksum

   // ...
   
   // Compare with stored checksum

   IF CalcChecksum = RecipeDB.CheckSum THEN

      RETURN := TRUE;  // Data is intact

   ELSE

      RETURN := FALSE; // Data may be corrupted

   END_IF;
END_FUNCTION

3. Safety and Redundancy Design

Safety Circuit Design

Voltage dip testing requires the safety circuit of the system to have sufficient anti-interference capability. In Siemens PLC systems, safety circuit design should consider:

1. Independent power supply: Key safety circuits use independent UPS or backup power

2. Selection of safety relays: Use safety relays with holding functions

3. Monitoring mechanisms: Real-time monitoring of power status, timely response to anomalies

// Safety circuit status monitoring function block

FUNCTION_BLOCK "FB_SafetyCircuitMonitor"

{ S7_Optimized_Access := 'TRUE' }

VERSION : 0.1

   VAR_INPUT 

      PowerSupplyOK : Bool;       // Normal power status signal

      SafetyRelayFeedback : Bool; // Safety relay feedback signal

   END_VAR

   VAR_OUTPUT 

      SystemSafe : Bool;          // System safety status

      PowerAbnormal : Bool;       // Power abnormal flag

      SafetyRelayError : Bool;    // Safety relay error

   END_VAR

   VAR 

      PowerStatus : Bool;         // Power status record

      EdgeDetect : Bool;          // Edge detection

   END_VAR


BEGIN

   // Power abnormal detection

   IF PowerStatus <> PowerSupplyOK THEN

      EdgeDetect := TRUE;

   ELSE

      EdgeDetect := FALSE;

   END_IF;
   PowerStatus := PowerSupplyOK;
   
   // Power dip detection

   IF EdgeDetect AND NOT PowerSupplyOK THEN

      PowerAbnormal := TRUE;
      // Warning or logging functions can be added

   END_IF;
   
   // Manual reset of power abnormal flag (may be needed in practical applications)
   // ...
   
   // Safety relay status monitoring

   SafetyRelayError := NOT SafetyRelayFeedback;
   
   // Comprehensive judgment of system safety status

   SystemSafe := PowerSupplyOK AND NOT SafetyRelayError;
END_FUNCTION_BLOCK

Redundancy Control Strategies

For critical systems, redundancy control is an effective strategy to cope with voltage dips:

1. CPU redundancy: Use redundant controllers such as S7-400H/S7-1500H

2. Power redundancy: Dual power input modules with automatic switching mechanisms

3. Communication redundancy: Redundant network topology and communication paths

4. I/O redundancy: Redundant acquisition and control of key signals

Fail-Safe Mechanisms

The system should have a complete fail-safe mechanism to ensure safe exit or recovery after voltage dips:

1. Definition of safe states: Clearly define the safe states of each device

2. Automatic recovery strategies: Design recovery processes based on different scenarios

3. Manual intervention interfaces: Provide interfaces and processes for operator intervention

Safety Level Assessment

The safety level assessment of the system after voltage dips should include:

1. Functional safety evaluation: Based on standards such as IEC 61508/61511

2. Reliability analysis: MTBF (Mean Time Between Failures) calculation

3. Risk assessment: Consideration of failure probability and severity of consequences

4. User Interface Design

Interface Layout Description

The dedicated interface for voltage dip testing should be designed to be clear and easy to operate:

1. Test control area: Parameter settings, start/stop buttons

2. Real-time monitoring area: Current test status, voltage curve

3. Result analysis area: Test records, performance indicators

4. System status area: Key device status, alarm information

Parameter Setting Description

The user interface should provide intuitive parameter setting functions:

1. Test level selection: Preset different intensity test schemes

2. Custom parameters: Dip amplitude, duration, repeat counts, etc.

3. Save/load configuration: Management function for test configurations

Operation Monitoring Description

Real-time monitoring is key to voltage dip testing:

1. Waveform display: Real-time display of voltage change curves

2. Status indication: Test phase, timer, completion rate

3. Key parameters: Real-time recording of system response data

Alarm Handling Description

A complete alarm mechanism ensures the safe conduct of tests:

1. Test exception alarms: Device response timeout, communication interruption, etc.

2. Safety limit alarms: Warnings for operations exceeding safety limits

3. Alarm records: Detailed alarm history and handling suggestions

5. Data Management and Storage

Parameter Configuration Table

The parameter configuration for voltage dip testing should be systematically managed:

1. Standard test configuration: Test parameter sets that comply with industry standards

2. Device-specific configuration: Customized parameters for different devices

3. User-defined configuration: Flexible parameter definition mechanism

Operational Data Recording

Recording and storage of test process data:

1. Time series data: Voltage changes, device responses

2. Event records: System status changes, abnormal events

3. Performance indicators: Recovery time, stability scores

Alarm Information Management

The system should establish a complete alarm management mechanism:

1. Alarm classification: Categorized by severity

2. Alarm records: Detailed timestamps and contextual information

3. Alarm statistics: Frequency analysis and pattern recognition

Data Backup Strategy

Ensure the safety and reliability of test data:

1. Regular backups: Automatic periodic backup mechanism

2. Event-triggered backups: Automatic backups before and after important tests

3. Multi-level storage: Combination of local and remote backups

Voltage dip testing is an indispensable part of industrial system validation, and proper implementation can significantly improve system reliability. Feel free to share your implementation experiences or technical questions in the comments section.