• Question 1: What are the three types of signals in the I2C bus during data transmission? (1) Start signal: When SCL is high, SDA transitions from high to low to start data transmission. (2) Stop signal: When SCL is high, SDA transitions from low to high to end data transmission. (3) Acknowledge signal: The receiving IC sends a specific low pulse to the transmitting IC after receiving 8 bits of data, indicating that the data has been received. The CPU sends a signal to the controlled unit and waits for an acknowledgment signal from the controlled unit. After receiving the acknowledgment signal, the CPU decides whether to continue transmitting signals based on the actual situation. If no acknowledgment signal is received, it is judged that the controlled unit has failed.

• Question 2: How to configure the I2C master mode port? Hardware mode: Alternate function open-drain output, neither pull-up nor pull-down. (Fast mode: 400 Kbit/s) Software simulation: Push-pull output, configure pull-up resistor.

• Question 3: I2C arbitration mechanism? Refer to: S5PV210 Development – How Much Do You Know About I2C? (3) The I2C arbitration mechanism is straightforward once you understand the wired-AND principle. Simply put, it follows the principle of “low level priority”, meaning whoever sends a low level first will gain control of the bus.

Answer:

Refer to: STM32 Development – PMIC, I2C Detailed ExplanationHardware mode: Communication speed setting: /* STM32 I2C Fast Mode */#define I2C_Speed 400000

/* Communication speed */I2C_InitStructure.I2C_ClockSpeed = I2C_Speed;

Software simulation: If no communication speed is set, how to calculate it?Through the I2C bus bit delay function i2c_Delay:

static void i2c_Delay(void)
{
	uint8_t i;

	/*
		The following time is obtained through the Anfu Lai AX-Pro logic analyzer test.
		When the CPU main frequency is 72MHz, running in internal Flash, MDK project not optimized
		When the loop count is 10, SCL frequency = 205KHz 
		When the loop count is 7, SCL frequency = 347KHz, SCL high level time 1.5us, SCL low level time 2.87us 
		When the loop count is 5, SCL frequency = 421KHz, SCL high level time 1.25us, SCL low level time 2.375us 
		
		IAR project compilation efficiency is high, cannot be set to 7
	*/
	for (i = 0; i < 10; i++);
}

Application scenarios: PMIC, accelerometer, gyroscope

• Question 1: How many lines does SPI need? The SPI interface generally uses 4 lines for communication: MISO master device data input, slave device data output. MOSI master device data output, slave device data input. SCLK clock signal, generated by the master device. CS slave device chip select signal, controlled by the master device.

• Question 2: What are the four modes of SPI communication? SPI has four working modes, which differ in SCLK, specifically determined by CPOL and CPHA. (1) CPOL: (Clock Polarity), clock polarity: SPI’s CPOL indicates whether the level of SCLK is low (0) or high (1) when idle: CPOL=0 means idle is low, so when SCLK is active, it is high (active-high); CPOL=1 means idle is high, so when SCLK is active, it is low (active-low);

(2) CPHA:(Clock Phase), clock phase: The phase corresponds to the data sampling on which edge (first or second), 0 corresponds to the first edge, 1 corresponds to the second edge. For: CPHA=0, it indicates the first edge: for CPOL=0, idle is low, the first edge is from low to high, so it is the rising edge; for CPOL=1, idle is high, the first edge is from high to low, so it is the falling edge; CPHA=1 indicates the second edge: for CPOL=0, idle is low, the second edge is from high to low, so it is the falling edge; for CPOL=1, idle is high, the first edge is from low to high, so it is the rising edge;

• Question 3: How to determine which mode to use? (1) First confirm the SCLK polarity required by the slave, whether it is low or high when not working, thus confirming CPOL as 0 or 1. Looking at the schematic, we set the idle state of the serial synchronous clock to high, so we choose SPI_CPOL_High. That is, CPOL is 1 (2) Then confirm from the slave chip datasheet’s timing diagram whether the slave chip samples data on the falling or rising edge of SCLK. Translate: W25Q32JV accesses via the SPI compatible bus, which includes four signals: serial clock (CLK), chip select (/CS), serial data input (DI), and serial data output (DO). The standard SPI instruction uses the DI input pin to serially write instructions, addresses, or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. Supports SPI bus operations in mode 0 (0,0) and 3 (1,1). Modes 0 and 3 concern the normal state of the CLK signal when the SPI bus master is in standby and no data is being transmitted to the serial Flash. For mode 0, the CLK signal is typically low at the falling and rising edges / CS. For mode 3, the CLK signal is typically high at the falling and rising edges of /CS. Since the idle state of the serial synchronous clock is high, we choose the second edge transition, thus selecting SPI_CPHA_2Edge. That is, CPHA is 1 namely, we choose mode 3 (1,1).

Answer:

Refer to: STM32 Development – Detailed Explanation of W25Q32JV SPI FlashRefer to: Detailed Explanation of CPOL and CPHA in SPIApplication scenarios: SPI Flash, W25Q32 memory capacity 32Mb (4M x 8), i.e., 4M byte

• Question 1: Summarize CAN? The CAN controller determines the bus level based on the voltage difference between CAN_L and CAN_H. The bus level is divided into dominant and recessive levels, one of which is sent by the sender by changing the bus level to send messages to the receiver.

• Question 2: Steps to initialize CAN configuration? (1) Configure the multiplexing function of the relevant pins, enable the CAN clock (2) Set the CAN operating mode and baud rate, etc. (CAN initialization loopback mode, baud rate 500Kbps) (3) Set the filter

• Question 3: CAN data transmission format? CanTxMsg TxMessage; TxMessage.StdId=0x12; // Standard Identifier TxMessage.ExtId=0x12; // Set extended identifier TxMessage.IDE=CAN_Id_Standard; // Standard frame TxMessage.RTR=CAN_RTR_Data; // Data frame TxMessage.DLC=len; // Data length to be sent Send 8 bytes for(i=0;i<len;i++) TxMessage.Data[i]=msg[i]; // data

Answer:

Refer to: STM32 Development – Detailed Explanation of CAN Bus

• Question 1: What is DMA? Direct Memory Access (DMA) is used to provide high-speed data transfer between peripherals and memory or between memory and memory. Data can move quickly through DMA without CPU intervention, saving CPU resources for other operations.

• Question 2: How many DMA transfer modes are there? DMA_Mode_Circular Circular mode DMA_Mode_Normal Normal buffer mode Application scenarios: GPS, Bluetooth, both use circular acquisition, DMA_Mode_Circular mode.

Answer:

Refer to: STM32 Development – Detailed Explanation of DMA

A relatively important function, obtaining the current remaining data size, based on the set receive buffer size minus the current remaining data size, to get the current received data size.

• Question 1: Describe the interrupt handling process? (1) Initialize the interrupt, set the trigger method to rising edge/falling edge/both edges. (2) Trigger the interrupt, enter the interrupt service function

• Question 2: How many external interrupts does STM32’s interrupt controller support? STM32’s interrupt controller supports 19 external interrupt/event requests: From the diagram, GPIO pins GPIOx.0~GPIOx.15 (x=A, B, C, D, E, F, G) correspond to interrupt lines 0 ~ 15. Additionally, the four EXTI lines are connected as follows: ● EXTI line 16 connects to PVD output ● EXTI line 17 connects to RTC alarm event ● EXTI line 18 connects to USB wakeup event ● EXTI line 19 connects to Ethernet wakeup event (only for interconnect products) Interrupt service function list: IO external interrupts in the interrupt vector table only allocate 7 interrupt vectors, meaning only 7 interrupt service functions can be used. EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler EXTI9_5_IRQHandler EXTI15_10_IRQHandler

Answer:

Refer to: STM32 Development – Detailed Explanation of External Interrupts

STM32 has 5 clock sources: HSI, HSE, LSI, LSE, PLL. ① HSI is a high-speed internal clock, RC oscillator, frequency is 8MHz, accuracy is not high. ② HSE is a high-speed external clock, can connect quartz/ceramic resonators, or connect external clock sources, frequency range is 4MHz~16MHz. ③ LSI is a low-speed internal clock, RC oscillator, frequency is 40kHz, providing low-power clock. ④ LSE is a low-speed external clock, connected to a quartz crystal with a frequency of 32.768kHz. ⑤ PLL is a phase-locked loop frequency multiplier output, whose clock input source can be selected as HSI/2, HSE, or HSE/2. The frequency multiplier can be selected from 2 to 16 times, but the maximum output frequency must not exceed 72MHz.

Answer:

Refer to: STM32 Development – Detailed Explanation of Clock System

• Question 1: How many types of low power modes are there? What are the wake-up methods?

Answer:

Answer:

There are 5 states: sleep state, ready state, running state, waiting state (waiting for a certain event to occur), and interrupt service state.

The 5 state transition relationships of UCOSII tasks:

• Question 1: Briefly describe the functional characteristics of the STM32 ADC system? (1) 12-bit resolution (2) Automatic calibration (3) Programmable data alignment (conversion results support left or right alignment stored in 16-bit data registers) (4) Single and continuous conversion modes

Refer to: STM32 Development – Detailed Explanation of ADC

• Question 1: Briefly describe the basic process of setting the system clock? (1) Enable HSE, wait for it to be ready, then set Flash wait operations. (2) Set AHB, APB1, APB2 prescaler coefficients to determine their relationship with the system clock. (3) Set CFGR register to determine PLL clock source and multiplication factor (HSE external 8M * 9 times = 72MHz). (4) Enable PLL, switch the system clock source to PLL.

• Question 1: What are the causes? (1) Array out-of-bounds operations; (2) Memory overflow, accessing out of bounds; (3) Stack overflow, program runaway; (4) Interrupt handling errors;

• Question 2: How to handle it? (1) Find the address remapping of HardFault_Handler in startup_stm32f10x_cl.s and rewrite it, making it jump to the HardFaultHandle function. (2) Print to check the registers R0, R1, R2, R3, R12, LR, PC, PSR. (3) Check the Fault status register group (SCB->CFSR and SCB->HFSR)

Refer to: STM32 Development – HardFault_Handler Handling Refer to: Cortex-M3 and Cortex-M4 Fault Exception Applications – Basic Knowledge

• Question 1: What method does sim7600 TTS speech use?

Answer:

(1) Use unicode encoding to synthesize voice AT+CTTS=1,”6B228FCE4F7F75288BED97F3540862107CFB7EDF” The content is “Welcome to the voice synthesis system”, the module sends and receives Chinese SMS using unicode encoding, so it is easy to read SMS aloud; (2) Directly input text, ordinary characters use ASCII code, Chinese characters use GBK encoding. AT+CTTS=2,”Welcome to the voice synthesis system”

• Question 1: Given that the STM32 system clock is 72MHz, how to set the relevant registers to achieve a 20ms timer?

Answer:

Refer to: STM32 Development – Systick Timer By SysTick_Config(SystemCoreClock / OS_TICKS_PER_SEC)) // 1ms timer

Where:

uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
#define SYSCLK_FREQ_72MHz  72000000
#define OS_TICKS_PER_SEC       1000    /* Set the number of ticks in one second

If 20ms is needed, a global variable can be set, initialized to 20, so that each time the SysTick interrupts, this global variable reduces by 1, until it reaches 0, meaning the SysTick interrupts 20 times, totaling 20ms. Thus, a 20ms timer is achieved.

• Question 1: How to run if there are two tasks with the same priority?

Answer:

Make the priority of the task obtaining the semaphore temporarily elevated to one level higher than the highest priority of all tasks during the use of shared resources, so that this task is not interrupted by other tasks, allowing it to quickly use and release the shared resources, and then restore the task to its original priority level after releasing the semaphore.