When it comes to pointers, it is impossible to separate them from memory. People who learn pointers can be divided into two types: those who do not understand the memory model and those who do. Those who do not understand typically think of pointers as “pointers are the address of a variable” and are quite … Read more
Follow to see more great articles like this~ Multi-size THP creation, two different ways By Jonathan CorbetFebruary 13, 2025Gemini-1.5-flash translationhttps://lwn.net/Articles/1009039/ Huge pages (巨页) can enhance the performance of many programs, but they can also bring adverse performance impacts. In recent years, multi-size transparent huge pages (mTHPs) (多尺寸透明巨页) have increasingly been seen as a compromise that … Read more
1 Stage 1 Page Table Attributes (Attribute fields in stage 1 VMSAv8-64 Block and Page descriptors) PBHA, bits[62:59]: for FEAT_HPDS2 XN or UXN, bit[54]: Execute-never or Unprivileged execute-never PXN, bit[53]: Privileged execute-never Contiguous, bit[52]: The translation table entry is contiguous and can exist in a TLB Entry DBM, bit[51]: Dirty Bit Modifier GP, bit[50]: for … Read more
The Memory Systems defined by ARMv8-A mainly unfold from three parts: Memory types, Memory attributes, and Barriers, which are introduced one by one below. 1. Memory types The ARMv8-A architecture defines two mutually exclusive memory types: Normal and Device. All memory regions are configured as one of these two types. 1.1 Normal memory Normal memory … Read more
Cache coherency Cacheability Normal memory can be set as cacheable or non-cacheable, and can be set separately for inner and outer. Shareability If set to non-shareable, that segment of memory is only used by a specific core. If set to inner shareable or outer shareable, it can be accessed by other observers (other cores, GPU, … Read more
Real-Time Memory Management Enhances Memory Operation Efficiency Segger Embedded Studio for RISC-V recently updated to version v6.22a, utilizing real-time memory management technology. This technology improves the efficiency of memory allocation and deallocation, reducing response time and meeting the hard real-time requirements for applications written in C++. The new version supports all common 32-bit and 64-bit … Read more
February 13, 2025 The primary benefit from subscribing to LWN is helping to keep us publishing, but, beyond that, subscribers get immediate access to all site content and access to a number of extra site features. Please sign up today! The primary benefit from subscribing to LWN is helping us maintain our publishing, but beyond … Read more
So far, we have learned that pointers should point to addresses of the same type specified in their declaration. For example, if we declare an int pointer, then this int pointer cannot point to a float variable or other types of variables; it can only point to int type variables. To solve this problem, we … Read more
Figure 2: The Role of MMU MCUs have an address set known as the virtual address range. For example, the virtual address range for Cortex-M 32-bit is 0 ~ 0xFFFFFFFF (4G address space). When this controller addresses a 256M memory, its usable address range is limited to 0 ~ 0x0FFFFFFF (256M). 1. In processors without … Read more
Friends with extensive project development experience must have encountered issues with memory overflow. How do you analyze such problems? The previous article detailed the map files in IAR, explaining how to analyze and understand the content of map files in IAR. This article will similarly discuss the contents of map files in MDK-ARM. Output Map … Read more