The Memory Systems defined by ARMv8-A mainly unfold from three parts: Memory types, Memory attributes, and Barriers, which are introduced one by one below. 1. Memory types The ARMv8-A architecture defines two mutually exclusive memory types: Normal and Device. All memory regions are configured as one of these two types. 1.1 Normal memory Normal memory … Read more
01. How many MMUs are there in a large system? 02. How many Translation regimes are there in an ARM Core? 03. What are the differences among EL1&0 Translation regime Stage 2, EL2 Translation regime Stage 1, and EL2&0 Translation regime Stage 1? 04. What is special about the TTBR1EL2 register, and who uses this … Read more
Click the card below to follow Arm Technology Academy This article is selected from the “Arm Technology Blog” column of the Jishu Community, authored by RC. This article mainly helps to understand the Armv8 memory system. Original link: https://stdrc.cc/post/2021/08/23/armv8-memory-system/ Cache coherency Cacheability Normal memory can be set as cacheable or non-cacheable, and can be set … Read more
Click the card below to follow Arm Technology Academy This article is selected from the Extreme Technology column “IC Design”, authorized to be reprinted from the WeChat public account Old Qin Talks Chips. This article will briefly study the Cortex-A series of the Armv8 architecture. In previous articles, Armv8-A has often been mentioned. So what … Read more
Learning Methods Scan to FollowLearn Embedded Together, learn and grow together Learning the Arm architecture versions v8 and v9 requires a deep understanding of several key concepts and mechanisms, including GIC (interrupt controller), exception handling, MMU (memory management unit), memory management, cache, TrustZone security architecture, security, and exclusive mechanisms. Here is an efficient learning method … Read more
In ARMv8, memory is divided into two types:Normal memory and Device memory, where Normal memory is suitable for most of the memory in the system, while Device memory is used for memory utilized by peripherals. 1. Normal Memory The Normal memory type attributes apply to most memory in the system. It indicates that the architecture … Read more
ver0.3 Introduction In previous articles, we introduced the ARM architecture’s interrupt controller GIC, which maintains a state machine for each interrupt signal. This interrupt state machine supports four states: Inactive, Pending, Active, and Active and Pending. The GIC maintains the status of each signal through internal registers and performs state transitions under relevant trigger conditions. … Read more
Cache coherency Cacheability Normal memory can be set as cacheable or non-cacheable, and can be set separately for inner and outer. Shareability If set to non-shareable, that segment of memory is only used by a specific core. If set to inner shareable or outer shareable, it can be accessed by other observers (other cores, GPU, … Read more
The ARM architecture can be traced back to 1985, but it has not remained static. Instead, it has undergone massive development since the early ARM cores, with each step adding features and functionalities: ARMv4 and Earlier Versions These early processors only used the ARM 32-bit instruction set. ARMv4T The ARMv4T architecture added the Thumb 16-bit … Read more
Thoughts: 1. When the SOC powers on, does only one core start, or do all cores start? 2. If only one core starts when the SOC powers on, where is the entry point for that core? 3. What is a cold boot? When is a warm boot used? In what scenarios would a warm boot … Read more