MSB: Most Significant Bit;
LSB: Least Significant Bit;
AHB: Advanced High-performance Bus;
VPB: VLSI Peripheral Bus connecting on-chip peripherals;
EMC: External Memory Controller;
MAM: Memory Accelerator Module;
VIC: Vector Interrupt Controller;
SPI: Full-Duplex Serial Interface;
CAN: Controller Area Network, a serial communication protocol;
PWM: Pulse Width Modulator;
ETM: Embedded Trace Macrocell;
CPSR: Current Program Status Register;
SPSR: Saved Program Status Register;
2. Notes on Using MAM:
Answer: When changing the MAM timing values, MAM must first be disabled by writing 0 to MAMCR, then the new value is written to MAMTIM. Finally, write the corresponding value for the required operation mode to MAMCR to enable MAM again.
For system clock frequencies below 20MHz, set MAMTIM to 001. For system clock frequencies between 20MHz and 40MHz, it is recommended to set Flash access time to 2cclk, and for system clock frequencies above 40MHz, it is recommended to use 3cclk.
3. Notes on Using VIC
Answer: If the code is running in on-chip RAM and the application needs to call interrupts, the interrupt vector must be remapped to Flash address 0x0. This is because all exception vectors are located at address 0x0 and above. This can be achieved by configuring the MEMMAP register (located in the system control module) to User RAM mode. User code is linked so that the interrupt vector table is loaded at 0x4000 0000.
4. ARM Boot Code Design
Answer: The ARM boot code directly programs the processor core and hardware controllers, generally using assembly language. The boot code typically includes:
Interrupt Vector Table
Initializing Memory System
Initializing Stack and Ports/Devices with Special Requirements
Initializing User Program Execution Environment
Changing Processor Mode
Calling Main Application
5. Difference Between IRQ and FIQ
Answer: IRQ and FIQ are two programming modes of ARM processors. IRQ refers to the interrupt mode, while FIQ refers to the fast interrupt mode. For FIQ, you must handle your tasks quickly and exit this mode. IRQ can be interrupted by FIQ, but IRQ cannot interrupt FIQ. To make FIQ faster, this mode has more shadow registers. FIQ cannot call SWI (Software Interrupt). FIQ must also disable interrupts. If an FIQ routine needs to re-enable interrupts, it is too slow and should be IRQ instead of FIQ.
6. ARM Processor’s Response Process to Exception Interrupts
Answer:
The ARM processor’s response process to exception interrupts is described as follows:
Save the current processor state, interrupt mask bits, and condition flags;
Set the corresponding bits in the Current Program Status Register CPSR;
Set the lr_mode register to the return address;
Set the Program Counter PC value to the interrupt vector address of the exception interrupt, and jump to the corresponding exception interrupt to execute.
7. Difference Between ARM Instructions and Thumb Instructions
Answer: In the ARM architecture, instructions in the ARM instruction set are 32-bit instructions with high execution efficiency. For application systems with a 16-bit data bus, the ARM architecture provides the Thumb instruction set. The Thumb instruction set is a subset of the ARM instruction set that has been re-encoded to a length of 16 bits. Typically, when the processor executes ARM programs, it is said to be in ARM state; when executing Thumb programs, it is said to be in Thumb state. The Thumb instruction set does not change the program design model of the ARM architecture but adds some constraints on that model. The operands of data processing instructions in the Thumb instruction set are still 32 bits, and the instruction addressing is also 32 bits.
8. What is ATPCS
Answer: To enable mutual calls between separately compiled C language programs and assembly programs, certain rules must be specified for calls between subroutines. ATPCS is the basic rule for subroutine calls in ARM programs and Thumb programs. These rules include register usage rules, data stack usage rules, parameter passing rules, etc.
9. Situations for Mixing ARM and Thumb Programs
Answer: Typically, Thumb programs are more compact than ARM programs, and for systems with 8-bit or 16-bit memory, using Thumb programs is more efficient. However, in the following situations, programs must run in ARM state, and thus ARM and Thumb programs need to be mixed.
In situations emphasizing speed, ARM programs should be used;
Some functions can only be completed by ARM programs, e.g., using or disabling exception interrupts;
When the processor enters an exception interrupt handler, the program state switches to ARM state, meaning that some instructions at the entry of the exception interrupt handler are ARM instructions, and then the program can switch to Thumb state as needed, before switching back to ARM state before returning from the exception interrupt program.
The ARM processor always starts execution in ARM state. Therefore, if you want to run a Thumb program in a debugger, you must add an ARM program header to that Thumb program, then switch to Thumb state to execute the Thumb program.
10. ARM Processor Operating Modes
Answer:
The ARM microprocessor supports seven operating modes, which are:
User Mode (usr): The normal program execution state of the ARM processor;
Fast Interrupt Mode (fiq): Used for high-speed data transfer or channel management;
External Interrupt Mode (irq): Used for general interrupt handling;
Supervisor Mode (svc): The protected mode used by the operating system;
Data Abort Mode (abt): Entered when data or instruction prefetch aborts, used for virtual storage and memory protection;
System Mode (sys): Runs privileged operating system tasks;
Undefined Instruction Abort Mode (und): Entered when an undefined instruction is executed, can be used for software simulation of hardware coprocessors.
11. Types of Exceptions Supported by ARM Architecture
Answer: The exceptions supported by the ARM architecture and their specific meanings are as follows (the numbers in parentheses indicate priority):
Reset ①: When the reset level of the processor is valid, a reset exception occurs, and the program jumps to the reset exception execution (exception vector: 0x0000,0000);
Undefined Instruction ⑥: When the ARM processor or coprocessor encounters an unprocessable instruction, an undefined exception occurs. This exception mechanism can be used for software simulation (exception vector: 0x0000,0004);
Software Interrupt ⑥: Generated by executing the SWI instruction, can be used for user mode program calls to privileged operation instructions. This exception mechanism can implement system function calls (exception vector: 0x0000,0008);
Instruction Prefetch Abort ⑤: If the address of the prefetch instruction does not exist, or the current instruction cannot access that address, the memory sends an abort signal to the processor, and the instruction prefetch abort exception occurs only when the prefetch instruction is executed (exception vector: 0x0000,000C);
Data Abort ②: If the address of the instruction for data access does not exist, or the current instruction cannot access that address, a data abort exception occurs (exception vector: 0x0000,0010);
IRQ④ (External Interrupt Request): When the processor’s external interrupt request pin is valid, and the I bit in CPSR is 0, an IRQ exception occurs. The system’s peripherals can request interrupt service with this exception (exception vector: 0x0000,0018);
FIQ③ (Fast Interrupt Request): When the processor’s fast interrupt request pin is valid, and the F bit in CPSR is 0, an FIQ exception occurs (exception vector: 0x0000,001C).
Note: The exception vector 0x0000,0014 is a reserved exception vector.
12. Memory Format Supported by ARM Architecture
Answer:
The memory formats supported by the ARM architecture are as follows:
Big-endian format: The high byte of word data is stored at the low address, and the low byte of word data is stored at the high address;
Little-endian format: Opposite to big-endian storage format, the high byte of data is stored at high address, and the low byte of data is stored at low address.
13. Summary of ARM Registers:
ARM has 16 32-bit registers (r0 to r15).
r15 acts as the program counter PC, r14 (link register) stores the return address of subroutines, and r13 stores the stack address.
ARM has a Current Program Status Register: CPSR.
Some registers (r13, r14) will generate new instances when an exception occurs, such as in IRQ processor mode, where the processor uses r13_irq and r14_irq.
ARM’s subroutine calls are fast because the return address of the subroutine does not need to be stored on the stack.
14. Reasons for Memory Remapping:
To ensure that the FIQ handler in Flash memory does not have to consider memory boundary issues caused by remapping;
To greatly reduce the use of SRAM and Boot Block vectors for handling code space segment boundary arbitration;
To provide space for jumps exceeding the single-word transfer instruction range to save constants.
Remapping in ARM refers to reallocating its memory address space mapping during program execution by writing to certain functional register bits. A typical application is that the application program is stored in Flash/ROM, initially starting from address 0, but the read time of this memory is longer than that of SRAM/DRAM, causing its internal execution frequency to be low. Therefore, generally, a section of code moves the code to SRAM/DRAM, then remaps the memory space to map the corresponding SRAM/DRAM to address 0, allowing the program to be executed at high speed.
15. Reason for Using LDR Instruction for Program Jumps in Exception Vector Table Instead of B Instruction:
The LDR instruction can jump across the entire address range, while the B instruction can only jump within a 32MB range before and after;
The chip has a Remap function. When the vector table is located in internal RAM or external memory, the B instruction cannot jump to the correct location.
16. Key Points on Phase-Locked Loop (PLL):
The PLL is turned off and bypassed during chip reset or power-down mode, and it does not automatically restore its settings after waking up from power-down;
The PLL can only be enabled by software;
After activation, the PLL must wait for it to lock before it can be connected;
If the PLL is not set correctly, it may lead to incorrect operation of the chip.
17. Differences Between ARM7 and ARM9:
The ARM7 core has a 0.9MIPS/MHz three-stage pipeline and von Neumann architecture; the ARM9 core has a five-stage pipeline and provides 1.1MIPS/MHz Harvard architecture.
The ARM7 does not have an MMU, while the ARM720T has an MMU; the ARM9 has an MMU, and the ARM940T only has a Memory Protection Unit, not a complete MMU.
The ARM7TDMI offers excellent performance-to-power consumption ratio. It includes the Thumb instruction set, fast multiplication instructions, and ICE debugging technology. The ARM9 has a higher clock frequency than ARM7 and uses Harvard architecture to distinguish between data and instruction buses.
18. Basic Operations of VIC are as Follows:
Answer: Set IRQ/FIQ interrupts; if it is an IRQ interrupt, it can be set as a vector interrupt and assign interrupt priority, otherwise it is a non-vector IRQ. Then, set the interrupt enable, and the corresponding address for the vector interrupt or the default address for non-vector interrupts. When an interrupt occurs, if it is an IRQ interrupt, read the vector address register, then jump to the corresponding code. When exiting the interrupt, write 0 to the vector address register to notify the VIC that the interrupt has ended. When an interrupt occurs, the processor will switch processing modes, and the related registers will also be mapped.
19. Notes on Using External Interrupts
After setting a pin as an external interrupt function, that pin is in input mode. Due to the lack of internal pull-up resistors, an external pull-up resistor must be connected to ensure the pin is not floating;
In addition to connecting the pin to the module, the VIC module must also be set up to generate external interrupts; otherwise, external interrupts can only reflect in the EXTINT register;
To make the device enter power-down mode and wake up through external interrupts, the software should correctly set the external interrupt function of the pin before entering power-down mode.
20. Basic Operation Methods of UART0
Set I/O connections to UART0;
Set the serial port baud rate (U0DLM, U0DLL);
Set the serial port operating mode (U0LCR, U0FCR);
Send or receive data (U0THR, U0RBR);
Check the serial port status word or wait for the serial port interrupt (U0LSR).
21. Basic Operation Methods of I2C
Answer:
Basic operation methods for I2C master:
Set I2C pin connections;
Set I2C clock rate (I2SCLH, I2SCLL);
Set as master and send start signal (I2CONSET’s I2EN, STA bit set to 1, AA bit set to 0);
Send slave address (I2DAT), control I2CONSET to send;
Determine bus status (I2STAT) and control data transmission;
Send end signal (I2CONSET).
Basic operation methods for I2C slave:
Set I2C pin connections;
Set its own slave address (I2ADR);
Enable I2C (I2CONSET’s I2EN, AA bit set to 1);
Determine SI bit or wait for I2C interrupt, waiting for master operation;
Determine bus status I2STAT and control data transmission.
22. Basic Operation Methods of PWM:
Connect PWM function pins for output, i.e., set PINSEL0, PINSEL1;
Set the clock division value of the PWM timer (PWMPR) to obtain the desired timer clock;
Set comparison match control (PWMMCR) and set the corresponding comparison value (PWMMRx);
Set PWM output mode and enable PWM output (PWMPCR) and latch enable control (PWMLER);
Set PWMTCR, start the timer, and enable PWM;
When changing the comparison value during operation, the latch enable must be set after changing.
When using dual-edge PWM output, it is recommended to use PWM2, PWM4, PWM6; when using single-edge PWM output, the high level is at the start of the PWM cycle, and low level after matching, using PWMMR0 as PWM cycle control, PWMMRx as duty cycle control.
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