As we all know, for an FPGA to operate, it must have a configuration file, which can come in various formats such as bin, bit, mcs, etc. So, how many ways are there to load these configuration files into the FPGA?There are mainly three methods: Master mode, Slave mode, and JTAG mode.Master: The FPGA acts as the master, and after powering on, it actively reads the configuration file from flash memory and loads it into the FPGA. This loading process is controlled by the FPGA.Slave: The FPGA acts as a slave, and after powering on, the host (CPU, MCU, etc.) sends the configuration file to the FPGA.The JTAG mode does not need an introduction, as it is an interface we commonly use during debugging.When configuring the FPGA, one point of concern is the configuration speed. There are two approaches to improve configuration speed.One is to increase the width of the configuration data. The higher the data width in the configuration interface, the more data can be transmitted in a single clock cycle. This further divides the master mode into: Master Serial mode and Master Parallel mode. It also further divides the slave mode into: Slave Serial mode and Slave Parallel mode.Master Serial mode: In master mode, one clock configures 1 bit of data.Master Parallel mode: In master mode, one clock configures 4 bits, 8 bits, or 16 bits of data.Slave Serial mode: The host sends the contents of the bit file to the slave FPGA one bit at a time.Slave Parallel mode: The host sends the contents of the bit file to the slave FPGA in 8 bits (or 4 bits, or 16 bits, or 32 bits).The second approach is to increase the configuration clock. The higher the clock, the faster the configuration speed.The clock is an oscillator inside the FPGA that starts oscillating after power-on, and this clock is output through the FPGA’s cclk pin. The frequency of this clock is also affected by the FPGA process, temperature, and voltage. This clock frequency is fixed and generally does not operate at very high speeds. If you want to increase the configuration clock frequency, you can switch the clock source to EMCCLK, which is provided by an external oscillator connected to the FPGA’s EMCCLK pin. This clock can be modified by us, allowing for the configuration of a higher frequency oscillator as needed.In summary, as shown in the figure below, there are 8 configuration modes for FPGAs.
Recently, a project required the use of Slave SelectMAP mode, and I will share more details about Slave Parallel mode later.Here, I would like to share the ug470 document, which provides detailed information about various FPGA configuration modes. You can check it out yourself.File shared via cloud drive: ug470_7Series_Config.pdf Link: https://pan.baidu.com/s/1Bh_nD3ws3xurjPYWM5HmoA?pwd=t15v Extraction code: t15v