1. Introduction to GD32 Microcontroller
Taking GD32F450ZKT6 as an example





The GD32F450ZKT6 on-chip RAM is divided into two parts: 192K + 64K = 256K
2. Introduction to memheap Management Algorithm
<span>The memheap management algorithm</span> is suitable for systems with multiple addressablenon-contiguous memory heaps. Using memheap memory management simplifies the usage when multiple memory heaps exist in the system: when there are multiple memory heaps in the system, the user only needs to initialize the required memheaps during system initialization and enable the memheap feature to conveniently combine multiple memheaps (which can be non-contiguous) for heap allocation in the system.
<span>Note: After enabling memheap, the original heap functionality will be disabled; the two can only be selected by enabling or disabling RT_USING_MEMHEAP_AS_HEAP.</span>

Default system heap initialization function – default usage
void rt_system_heap_init(void* begin_addr, void* end_addr);
This function will use the memory space of the parameters <span>begin_addr, end_addr</span> as the memory heap.

Non-contiguous memory heap initialization function – user usage When using memheap heap memory, it must be initialized during system initialization.
rt_err_t rt_memheap_init(struct rt_memheap *memheap, const char *name, void *start_addr, rt_uint32_t size)
<span>If there are multiple non-contiguous memheaps, this function can be called multiple times to initialize them and add them to the memheap_item linked list.</span>

3. Development Environment
System: RT-Thread 5.0.0 or 4.1.1 Microcontroller: GD32F450ZKT6
4. System Configuration
Select <span>memheap management algorithm</span>


5. Code Modifications
Add macro definitions

#ifdef RT_USING_MEMHEAP_AS_HEAP #define GD32_SRAM2_SIZE 64*1024 #define GD32_SRAM2_BEGIN (0x10000000u) #define GD32_SRAM2_END (0x10000000 + GD32_SRAM2_SIZE)#endif
Define memheap control block

#ifdef RT_USING_MEMHEAP_AS_HEAP static struct rt_memheap ccm_heap;#endif
Call <span>rt_memheap_init</span> function to initialize

/** * This function will initialize the GD32 board. */void rt_hw_board_init(){ /* NVIC Configuration */#define NVIC_VTOR_MASK 0x3FFFFF80#ifdef VECT_TAB_RAM /* Set the Vector Table base location at 0x10000000 */ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);#else /* VECT_TAB_FLASH */ /* Set the Vector Table base location at 0x08000000 */ SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);#endif SystemClock_Config();#ifdef RT_USING_COMPONENTS_INIT rt_components_board_init();#endif#ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME);#endif#ifdef BSP_USING_SDRAM rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);#else rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);#endif#ifdef RT_USING_MEMHEAP_AS_HEAP rt_memheap_init(&ccm_heap, "ccm", (void *)GD32_SRAM2_BEGIN, GD32_SRAM2_SIZE);#endif}
6. Testing
Compile, download to the development board, and the test results are as follows:

References:
RT-Thread Memory Management