Source: ICisC Nanjing Integrated Circuit Industry Service Center
1. Concept: SPI: Serial Peripheral Interface
The SPI flash is a flash storage device that operates through a serial interface. Flash memory is categorized into two types based on its internal storage structure: NOR flash and NAND flash. Here, SPI flash belongs to NOR flash!
SPI flash has slower read/write speeds and a limited number of write cycles, generally used for storage that is not frequently changed.
Early Norflash interfaces were in parallel form, meaning the data and address lines were connected side by side to the IC pins. However, it was later found that NOR flash of different capacities could not be hardware compatible (the number of data lines and address lines varies), and the packaging was relatively large, occupying significant PCB space. Therefore, it was gradually replaced by SPI (Serial Interface) NOR flash. Nowadays, many people refer to NOR flash directly as SPI flash.
2. Introduction to SPI FLASH Read/Write
Operations on flash chips generally include erasing, programming, and reading the flash chip. The SPI flash chips from major manufacturers are quite similar, and the operation commands are mostly unchanged. When we get a chip, we need to pay special attention to the chip’s capacity and operation partition, etc.
In fact, whether erasing, programming, or reading the chip, we can generally follow this routine: write command—write address—write (read) data. As clearly shown in the timing diagram below, we first pull the chip select signal low, then sequentially write the command, address, and data to operate on the FLASH chip.
By mastering the above methods, you can easily operate on the SPI flash chip. However, for low-level operations like timing, continuous learning and accumulation are required. Whether using FPGA or MCU, the ultimate goal is to generate timing signals. As long as you take the time to understand it carefully, all problems will be resolved.
3. Precautions
1. Different SPI FLASH chips may provide various erasure methods: sector erase (4KBytes), half-block erase (32KBytes), block erase (64KBytes), chip erase.
2. Different SPI FLASH chips may offer various programming methods (i.e., writing data): page programming (256Bytes), sector programming (4KBytes).
3. If the SPI FLASH has been erased, writing data like 0xFF is not very meaningful because its characteristic is that the data is 0xFF after erasure.
4. When writing to flash, you can only change data (bit) from 1 to 0.
5. The characteristic of traditional EEPROM is that it can randomly access and modify any byte, allowing you to write 0 or 1 to each bit. However, when writing to flash, you can only change data (bit) from 1 to 0. Traditional EEPROM capacities are limited due to cost, and it is rare to exceed 512K.
6. NOR Flash has relatively small capacity, high cost, and generally no bad blocks. The data and address lines are separate, allowing for random addressing and reading of any byte, but erasing still needs to be done by blocks. NAND FLASH has a large capacity, low cost, and bad blocks often occur, but bad blocks can be marked to allow software to skip them. The data and address lines are multiplexed, allowing for block erasing and page reading.
4. Issues in Project Practice
In a project requiring SPI flash, I encountered three memorable issues while using this 4MB SPI flash, which I record here as reminders.
Issue 1: We know that SPI flash can operate in master-slave mode, where the master is usually an MCU or similar device, while the slave is an SPI device. This small system of mine is no exception.
Moreover, the MCU has a built-in SPI controller, and the wiring method is still a four-wire solution: SCK, CS, DO, DI. While reviewing the manual, due to my negligence, I read the description: “user can decide the SPICS configuration in the master mode, if P_IO_Ctrl[10] set 1, the IOA[12] as GPIO function, if P_IO_Ctrl[10] set 0, the IOA[12] as SPICS hardware function.” At that moment, I did not fully comprehend this statement and mistakenly thought I needed to set P_IO_Ctrl[10] to 0 before using the SPI flash, which was incorrect.
Since we are operating the slave SPI device through the MCU, we first need the MCU side to select the SPI device. From the master’s perspective, we only need a GPIO signal line connected to the slave’s CS pin and outputting low level to select this slave. This is because, from the slave’s perspective, the MCU also acts as a slave. If another MCU controls this slave, then during SPI initialization, P_IO_Ctrl[10] needs to be set to 0.
Issue 2: A programmer is needed to write content to the SPI flash, and I used the SuperPro from Xilite, but I made an error in the programming steps, forgetting that I must erase before programming. After some investigation, it seems that it is similar to the NOR flash medium, where erasing sets all bits to 1, and during programming, you can only set the corresponding positions to 0 as needed.
Issue 3: When using an MCU’s SPI controller interface to connect to the SPI flash, I did not cross-connect, meaning the MCU’s DI should connect to the SPI’s DO, and the MCU’s DO should connect to the SPI’s DI.
Public Account ID: imecas_wx
