Author: Sifan
Personal WeChat: pulloff888
MIPI (Mobile Industry Processor Interface) was established in 2003 by companies like ARM, Nokia, ST, TI, etc. (www.mipi.org). The goal is to standardize the internal interfaces of mobile phones such as camera, display interfaces, RF/baseband interfaces, etc., thus reducing the complexity of mobile phone design and increasing design flexibility. CSI aims to provide a high-speed serial interface between high-definition cameras and application processors. For example, the CSI protocol is currently used between the camera and CPU in smartphones. The widely used version is its second version, CSI-2, while the latest version is CSI-3. As for whether CSI-1 exists or has ever existed, it is currently unverified; at least it cannot be found on the MIPI official website. There are many interface standards between sensors and microcontrollers, such as UART protocol, I2C, I2S, SPI, SDIO, etc. Various parallel interfaces related to camera sensors and displays have emerged, and the multitude of different interface standards leads to confusion during design. Meanwhile, using parallel interfaces usually involves over 10 signals for camera sensors and up to 20 for displays, which can cause transmission congestion. Moreover, parallel interfaces have no advantages in terms of cost, size, weight, or reliability of each signal (every signal and node can potentially fail). MIPI is not a single interface or protocol but includes a set of protocols and standards to meet the unique requirements of various subsystems (image subsystems [camera and display], storage subsystems, wireless subsystems, power management subsystems, low bandwidth subsystems [audio, keyboard, mouse, Bluetooth]). Traditional interfaces are generally related to multiple physical layers, while MIPI interfaces only connect to the D-PHY or M-PHY physical layers when needed.
CSI-2 protocol can use the D-PHY physical layer protocol consistent with DSI or C-PHY as the physical layer protocol. In contrast, CSI-3 can only use M-PHY as the physical layer protocol, meaning that CSI-2 and CSI-3 are incompatible!
DSI defines a high-speed serial interface located between the processor and the display module.
CSI defines a high-speed serial interface located between the processor and the camera module.
D-PHY: provides the physical layer definition for DSI and CSI
Generally, CSI-2 and DSI require no more than 6 signal lines, and the number of signals depends on the number of lines used by the designer. Additionally, CSI-2 and DSI share a common physical interface called D-PHY, designed to improve efficiency, reduce power consumption, and minimize EMI.
Mipi CSI is mainly for cameras. The Mobile Industry Processor Interface, besides ground lines, generally has 1 pair of I2C communication pins, 1 pair of MIPI differential clock pins, and 1-4 pairs of MIPI differential data signal pins.
MIPI CSI2‘s layered structure
MIPI CSI2’s layering method has several types; according to the MIPI alliance specifications, CSI2 can be divided into 5 layers: application layer, packetizing/unpacking layer, low-level protocol layer, channel management layer, and physical layer.
Protocol structure terminology explanation:
In detail, the working sequence of the link is as follows:
First, the raw image data undergoes corresponding image processing at the application layer, including white balance, noise reduction, color restoration, etc.
The processed data enters the packetizing layer for data segmentation and recombination, then it is sent to the protocol layer. The protocol layer generates a packet header based on the data type and produces a checksum for the packet tail based on the data content. Afterward, the header, the data itself, and the tail are combined and sent to the channel management module.
The channel management module reasonably allocates data to each channel according to the channel gating situation, and then the data undergoes analog-to-digital conversion before entering the physical layer for transmission. The receiving end unpacks the original image data in reverse order after receiving the data from the physical layer.
MIPI CSI2’s physical connection
Besides ground lines, MIPI CSI2 generally has 1 pair of I2C communication pins, 1 pair of MIPI differential clock pins, and 1-4 pairs of MIPI differential data signal pins.
In typical applications, the sender completes various processing of the image and packages the data according to protocol before transmitting the signal to the receiver via differential signal lines. The differential signal lines generally consist of one pair of clock differential lines and multiple pairs of data differential lines, with the number of data differential lines depending on the data transmission volume requirements. Generally, for mobile phones with 2 million to 5 million pixels, two pairs of differential data lines, i.e., two data channels, are used. However, when the camera pixels increase to 8 million or even 13 million, four data channels, i.e., four pairs of differential data lines, are typically used.
When interacting with external control signals, the I2C interface is used. The MIPI sender uses the I2C slave IP, and the control registers of the MIPI CSI-2 interface connect to the I2C slave. This way, external receiving devices can configure the internal registers of the MIPI sender via I2C, changing the duration of the internal state machine of the MIPI CSI-2 interface and the number of channels output at the end, or reading these registers during debugging for inspection, to determine the working status of the sender, and analyzing the sender’s operational state through the phenomena at the receiver.
MIPI CSI2‘s working modes
D-PHY has two transmission modes:
(1) HS High-Speed Transmission Mode, used for burst data transmission, synchronous transmission, where the signal is differential, voltage range is 100mv-300mv, and transmission speed range is 80-1000Mbps. In this mode, when the positive end of the differential line receives a 1.2V signal and the negative end receives a 0V signal, the receiver identifies it as 1. The opposite indicates 0.
(2) LP Low-Power Mode, used for control command transmission, asynchronous transmission, where the signal line is single-ended, voltage range is 0-1.2v, without a clock line; the clock is derived from the two data lines via XOR, with a speed of only 10Mbps. In this mode, when the positive end receives 300mV and the negative end receives 100mV, the receiver identifies it as 1. The opposite indicates 0.
MIPI CSI2‘s data packet format
MIPI CSI2 is a byte-oriented, packet-based protocol; it supports transmission of arbitrary data sizes through short and long packet formats. Each packet is separated by the EOT-LPS-SOT sequence.
LLP packets come in two types: long packets and short packets. Each packet transmission starts with SoT (start of transmission) and ends with EoT (end of transmission), with the gap in between being LPS (Low Power State).
MIPI CSI2‘s long packet format
The long packet of MIPI CSI2 mainly consists of a packet header, data packet, and packet tail. The packet header can be further divided into: data identifier, data packet size, and error correction code (ECC).
The data identifier is 1 byte, containing the virtual data channel number [7:6] and data type [5:0].
The data packet size is 2 bytes, indicating the length of the transmitted data in words.
The error correction code size is 1 byte, responsible for checking and correcting errors in the data packet transmission.
The size of the data packet can range from 0 to 65535 bytes.
The packet tail size is 2 bytes, used for checking the data load.
MIPI CSI2‘s short packet format
Compared to long packets, short packets do not have data packets and packet tails. The data identifier DI’s data type ranges from 0x00 to 0x0F. The WC field is the data field of the short packet, which can be user-defined. ECC is the checksum that can correct 1-bit errors and check 2-bit errors.
Differences between MIPI and DVP
MIPI is differential serial transmission, fast and resistant to interference.
Current mainstream phone modules use MIPI for transmission, utilizing 4 pairs of differential signals to transmit image data and 1 pair of differential clock signals; initially designed to reduce the number of connections between the LCD screen and the main control chip, it has since evolved to high speeds, supporting high-resolution displays, and is now predominantly MIPI interfaces. MIPI cameras have three power supplies: VDDIO (IO power), AVDD (analog power), DVDD (core digital power). Different sensor modules have different power supplies; AVDD can be 2.8V or 3.3V; DVDD typically uses 1.5V or higher, and different manufacturers have different designs. 1.5V may be provided by the sensor module or externally supplied; if external power is used, it is recommended to use external power, with a voltage greater than the internal DVDD; VDDIO voltage should match the level of the MIPI signal line; if the signal line is 2.8V, VDDIO should also supply 2.8V, and some sensor modules may not supply VDDIO, getting it from internal sources.
DVP is parallel transmission, slower, with lower bandwidth; it uses PCLK he sensor output clock, MCLK (XCLK) he external clock input, VSYNC rame synchronization, HSYNC
ow synchronization, D[0:11] he parallel data—can be 8/10/12bit data sizes. The DVP camera power supply is the same as MIPI. Here are the definitions of each signal pin:
PCLK: Pixel synchronization clock signal, with each PCLK corresponding to one pixel, can be 48MHz; for clock signals, they are usually packaged to reduce interference with other signals, and resistors and capacitors need to be added at the source to reduce overshoot and ringing, thereby minimizing interference with other signals.
MCLK (XCLK): External clock input, provided by the main control or crystal oscillator, determined by the sensor’s specifications, can be 24MHz;
VSYNC: Frame synchronization signal, one signal per frame, frequency is several tens of Hz (30Hz)
HSYNC: Row synchronization signal (frequency is several tens of kHz)
