Introduction:
This issue focuses on MIPI D-PHY testing, gathering firsthand experience from several senior engineers, summarized as follows:
1.
Introduction to MIPI
2.
Overview of MIPI D-PHY Technology
3.
MIPI D-PHY Physical Layer CTS Testing
4.
Challenges in MIPI D-PHY Testing
In Section 4, we summarize many challenges and precautions encountered in practical measurements, hoping to better assist everyone in completing MIPI D-PHY related testing.
1
Introduction to MIPI
The MIPI Alliance, or Mobile Industry Processor Interface, was established in 2003 by companies such as ARM, Nokia, ST, and TI to create open standards and specifications for mobile application processors. MIPI has become the most mainstream video transmission interface specification in the mobile field, with the most widely used protocols being MIPI D-PHY and MIPI C-PHY. Many modules in C-PHY are inspired by D-PHY, and both standards can share the same pins for dual-mode operation. MIPI M-PHY and A-PHY will be covered in more detail in our future articles.
Under the MIPI Alliance, various WorkGroups define a series of internal interface standards for mobile devices such as smartphones, including camera interfaces (CSI), display interfaces (DSI), interconnections between BBIC and RFIC (DigRF), and microphone/speaker interfaces (SLIMbus). MIPI technology is layered, including physical, protocol, and application layers, where the same PHY physical layer can carry different protocols. Below is the MIPI system block diagram and multimedia specifications:
Figure 1: MIPI System Framework (Source: MIPI Alliance official website)
Figure 2: MIPI Multimedia Specifications (Source: MIPI Alliance official website)
2
Overview of MIPI D-PHY Technology
MIPI has two interfaces that are most mature in application, with protocol layers of CSI-2 and DSI/DSI-2.
• Camera interface: CSI (Camera Serial Interface)
• Display interface: DSI (Display Serial Interface)
The physical layer (Phy Layer) of CSI-2 and DSI/DSI-2 is defined by a dedicated WorkGroup, and the currently adopted physical layer standards are D-PHY and C-PHY. Below is the technical evolution of D-PHY and a comparison of the technical characteristics of each version.
Figure: Source: MIPI Alliance
D-PHY realizes the interconnection between Camera/Display and AP (Application Processor), featuring high speed, low power consumption, and low cost. It is suitable not only for mobile applications but also for IoT. D-PHY provides a source-synchronous interface between master and slave, including one pair of unidirectional differential clocks, supporting SSC, and 1 to 4 pairs of unidirectional or bidirectional differential data lines. Data transmission uses DDR mode, meaning data is transmitted on both edges of the clock. Below is the Two Data Lane PHY Configuration of D-PHY:
Figure: D-PHY Two Data Lane PHY Configuration
D-PHY’s physical layer supports two operating modes: HS (High Speed) and LP (Low Power). In HS mode, low-voltage differential signals are used with termination, allowing for very high data rates (data rates of 80M to 1.5Gbps/without skew calibration, 1.5G to 2.5Gbps/with deskew calibration, 2.5G to 9G/with equalization); in LP mode, single-ended signals are used without termination, resulting in very low data rates (<=10Mbps), but correspondingly low power consumption as well, with EMI considerations limiting the slew-rate and drive current of generated signals. The optional supported alternate low-power mode uses terminated low-voltage differential signals, with a minimum forward data rate of 4Mbps and a reverse minimum of 1Mbps, while the maximum remains consistent with HS rates. The combination of HS and LP modes ensures that the MIPI bus can transmit large amounts of data (such as images) at high speeds when required while reducing power consumption when large data transfers are unnecessary.
Below is a diagram showing the signal levels in HS and LP modes, and below that is a waveform captured using an oscilloscope of MIPI D-PHY signals, clearly showing the HS and LP signals.
Figure 1: Signal Levels in HS and LP Modes
Figure 2: Oscilloscope Captured MIPI D-PHY Signals
Although the board-level design of MIPI D-PHY is simple, the internal architecture of MIPI chips and I/O technologies is very complex. The complexity is reflected in several aspects:
1) The MIPI communication architecture includes sending (typically master), receiving (typically slave), and interconnection channels.
Figure: MIPI D-PHY Point-to-Point Interconnection
2) Channel types include clock channels, unidirectional data channels, and bidirectional data channels. The transceiver channel module includes line interfaces, control/interface logic, and protocol interfaces. The control/interface logic can implement Escape mode encoding related to LP-TX, HS-Deskew, Sequences related to HS-TX, HS-RX can achieve data collection, HS-Deskew, and LP-RX can achieve decoding in control mode and Escape mode, while LP-CD for bidirectional data channels can implement conflict/competition detection.
Electrical aspects involve LP-TX implemented with slew-rate controlled push-pull circuits, HS-TX implemented with high-speed low-voltage differential driving circuits (optional support for half-swing mode for power saving/ rate exceeding 2.5Gbps requires 2 taps de-emphasis to overcome ISI effects), and HS-RX implemented with high-speed differential receiving circuits (can enable ZID impedance). Additionally, LP-RX circuits focus on low power consumption, requiring integration of hysteresis functions to reduce noise sensitivity.
Figure: Internal Composition and Electrical Implementation of Transceivers
3) The TLIS transmission line interconnection architecture supports different transmission