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Let’s talk about Xilinx’s MIPI solution. Here we take the ordinary 7 series as the discussion object, while Xilinx’s high-end KU+/MPSOC+ has already directly supported MIPI interface IO.
Since the MIPI signal is quite special, low power consumption should have been fully considered at the design stage, so the native signal level of MIPI supports HS and LP modes, working at different level standards:
From the image, it can be clearly seen that MIPI electrical signals exist in two level modes at the same time. If connected to the FPGA pins, it is obvious that the FPGA cannot support it. At the same time, the HS mode level standard is also not supported by the FPGA. Therefore, Xilinx provides two solutions to implement MIPI signal level conversion, which is detailed in document XAPP894, below only the MIPI DPHY Rx part is given.
In the case of high MIPI line rates, this method is not recommended.
When used to receive a camera, only the MC20901 is needed.
The premise of MIPI debugging is that you have correctly completed the sensor configuration. It is recommended to obtain a set of verified configurations from the internet or FAE to drive the sensor. This way, the focus of the debugging can be placed on the MIPI part. (To add, a concept I remember most from high school biology is: when conducting experiments, variables must be controlled, and only by satisfying the single variable repeated comparison experiment can issues be explained. However, in work, many times when problems arise, the positioning is often random guessing.)
Since using Xilinx’s MIPI RX Subsystem IP solution, the parts that users can configure are actually not many. However, this Subsystem is actually composed of 2 IPs, one is MIPI-DPHY, and the other is MIPI-CSI2 interface, and the two IPs are interconnected using a PPI interface.
MIPI DPHY receives bitstream data, and then restores the packet according to the frame format. The protocol has ECC verification for the packet, which has certain error recognition and correction capabilities. However, if the signal quality is poor and there are many errors, unrecoverable errors may occur, which will show as incorrect timing on the image leading to flying lines or even color noise. After synthesis is completed, open the synthesized schematic diagram, enter the MIPI DPHY part, mark the signals with the physical layer suffix ‘err’ for debugging, and then save to the xdc file for later debugging.
From the image, it can be seen that the ‘errorths’ signal in the Xilinx MIPI IP PPI interface is pulled high, indicating that there is a line loss situation. If this occurs and the physical layer error signals continue, after checking that there is no issue with the FPGA project itself, then consider whether there is a hardware problem.
This article is reproduced from Blog Garden:
https://blog.csdn.net/wuyanbei24/article/details/104603426/
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