Let’s talk about Xilinx’s MIPI solution. Here, we take the ordinary 7 series as the discussion object, while Xilinx’s high-end KU+/MPSOC+ already support MIPI interface IO directly.Due to the special nature of MIPI signals, low power consumption should be fully considered at the design stage. Therefore, the native signal levels of MIPI support both HS and LP modes, operating at different voltage standards:From the figure, it can be clearly seen that MIPI electrical signals exist in two voltage modes simultaneously. If connected to the FPGA pins, it is evident that the FPGA cannot support this. Moreover, the voltage standard of HS mode is also not supported by the FPGA. Therefore, Xilinx has provided two schemes to achieve MIPI signal level conversion, which is detailed in document XAPP894. Below, only the MIPI DPHY Rx part is provided.1. Resistor NetworkIn cases of higher MIPI line rate, this method is not recommended.2. External Chip MC20901When used for receiving a camera, only the MC20901 is needed.About MIPI DebuggingThe premise for MIPI debugging is that you have correctly completed the sensor configuration. It is recommended to obtain a set of verified configurations from the internet or FAE to drive the sensor. This way, the focus of debugging can be placed on the MIPI part. (To add, one concept I remember most from high school biology is: when conducting experiments, variables must be controlled, and only by satisfying the repeated comparison of a single variable can issues be explained. However, in work, many times when problems arise, the positioning is often just random guessing.)Since the Xilinx MIPI RX Subsystem IP solution is used, the parts that users can configure are actually quite limited. However, this subsystem is composed of two IPs: one is MIPI-DPHY, and the other is MIPI-CSI2 interface, and the two IPs are interconnected via PPI interface.MIPI DPHY receives the bitstream data and then recovers the packet according to the frame format. The protocol includes ECC checks for the packets, providing a certain ability to identify and correct errors. However, if the signal quality is poor and many errors occur, unrecoverable errors will appear, resulting in artifacts on the image, such as misalignment causing lines to appear or even color distortion. After synthesis is completed, open the synthesized schematic, enter the MIPI DPHY section, mark the signals with the suffix err in the physical layer for debugging, and then save them to the xdc file for later debugging.From the figure, it can be seen that the error signal errorths in the Xilinx MIPI IP PPI interface is pulled high, indicating that there is a row loss situation. If this occurs and the physical layer error signals continue, then after checking that the FPGA project itself is fine, hardware issues should be considered.
