The more emerging technologies flourish, the more RISC-V thrives. With advantages such as openness, customizability, scalability, and efficiency, RISC-V is accelerating its penetration into fields like generative AI, automotive electronics, and smart terminals, revitalizing the computing industry with new logic and ideas. Meanwhile, with the release of RVA23, RISC-V’s software ecosystem and cross-platform capabilities continue to improve, accelerating adaptation across the entire industry chain. At the fifth RISC-V China Summit held on July 17, reporters witnessed a series of “chip” trends.RVA23 Comes to Reality: Hardware Implementation and Toolchain Adaptation AccelerateFor a long time, cross-platform compatibility and software portability have been bottlenecks restricting the expansion of the RISC-V ecosystem. In October last year, the RISC-V International Foundation announced the formal approval of the RVA23 profile. This profile standardizes the implementation standards for 64-bit application processors, enabling them to run operating system stacks from standard binary operating system distributions, which is crucial for achieving software portability across hardware platforms and effectively avoiding vendor lock-in risks.At this year’s RISC-V Summit, attendees introduced a series of adaptation progress surrounding RVA23.Based on the profile specifications, developers also need RVA23 hardware solutions to obtain hardware support such as development boards. Krste Asanovic, Chief Architect of the RISC-V International Foundation, stated that RVA23 hardware is already on the way. “Many developers ask where the RVA23 hardware is; please be patient, soon there will be RVA23 hardware solutions, which is the first step in RISC-V’s long march. We will have a roadmap for the hardware and software ecosystem, allowing everyone to clearly understand where RISC-V is headed.”
At the same time, the RISC-V International Foundation will focus on long instructions greater than 32 bits, reserving more space for RISC-V’s performance improvement. “The fixed 32-bit instruction format will become an obstacle to the long-term evolution of RISC-V; other fixed 32-bit ISAs are already constrained in encoding space,” Krste Asanovic said. “RISC-V has included variable-length instructions from the beginning, and longer instructions help reduce code size, improve performance, and support an increasing number of data types.”RVA23 also brings more challenges to the co-simulation verification of RISC-V processors. Xu Yinan, a special research assistant at the Institute of Computing Technology, Chinese Academy of Sciences, stated that on one hand, the complexity of the RISC-V instruction set is rapidly expanding; for example, RVA23 has 33 mandatory extensions and an 830-page instruction set manual, which has doubled compared to 2019, and different RISC-V extensions have different verification requirements, leading to increased verification difficulty. On the other hand, the circuit simulation speed of processors—especially software-based simulation speed—decreases significantly as the processor scale increases.
To improve chip verification quality and efficiency, the industry is turning to hardware simulation platforms based on Emulator and FPGA, characterized by deploying the REF (Reference Model) in the Host environment, with soft and hardware (RTL-Host) communication at its core, using PCIe, Ethernet, InfiniBand, and other connection methods to transmit information between software (Host side) and hardware (RTL side), achieving orders of magnitude acceleration in circuit simulation. For example, the DiffTest framework maintained by the Xiangshan processor team has already supported hardware simulation acceleration.However, the Xiangshan team found that the communication overhead brought by the RTL-Host architecture limited the verification acceleration effect of DiffTest for complex processors like Xiangshan. To address this bottleneck, the Xiangshan team proposed SVM (Synthesizable Verification Method), mapping the entire REF onto FPGA or Emulator, allowing communication between REF and DUT (Design Under Test) to be completed on-chip, thus avoiding communication overhead.As the Xiangshan processor iterates to the third-generation architecture “Kunming Lake,” the number of cores has increased to 16, further increasing system complexity. For the large-scale cascading FPGA system verification of the Xiangshan Kunming Lake 16-core CPU, the Xiangshan team, in collaboration with EDA company Gongjian Soft, proposed a systematic multi-core processor FPGA verification methodology, including design migration and adaptation, maximizing the balance between compilation iteration efficiency and resource optimization, progressive startup strategies, and soft-hardware collaborative debugging techniques. Based on this methodology, the overall verification efficiency of the Kunming Lake 16-core version improved by about 40%, significantly shortening the product launch time, and key tasks such as clock conversion, automatic segmentation, and TDM IP binding can be handed over to EDA tools, allowing users to focus their valuable time on the project itself.Regarding the evolution path of RVA, Krste Asanovic revealed that the next version of RVA is tentatively named RVA30, expected to be released around 2030. The RISC-V community will first promote the implementation of RVA23, then gradually transition to RVA30. During this process, small version updates such as RVA23.1 and RVA23.2 will be released, adding some minor options to enhance the functionality upgrades of future RVA30.Expanding the Circle: CUDA Will Adapt to RISC-VIn 2024, the global shipment of chips based on the RISC-V instruction set will reach hundreds of billions, with a significant portion integrated into embedded systems. Now, RISC-V’s circle is expanding, and it is expected to play a more prominent role in higher-performance computing architectures.NVIDIA ships over a billion chips each year that integrate RISC-V microcontrollers. Now, NVIDIA is working on a deeper integration with RISC-V.“CUDA has been deployed on x86 and Arm instruction sets, but not yet on RISC-V. However, we are conveying a message to the outside world—we want to port CUDA to the RISC-V architecture,” said Frans Sijstermans, Vice President of NVIDIA.
Frans Sijstermans introduces NVIDIA’s progress on RISC-VIn promoting the adaptation of CUDA to RISC-V, Frans Sijstermans noted that there are three areas of work that need to be strengthened.First, on the technical specifications, the RVA23 architecture profile and server SoC specifications have been approved, but there is still a lack of server platform specifications and support for performance event monitoring, memory tagging, confidential virtual machines, matrix operations, etc.Second, on the software side, 75 software packages are already supported for adaptation on the RISC-V International Foundation’s official website, but there is still room for improvement in performance optimization, ecosystem maturity, and high-level application stacks.Third, regarding CPUs, the currently available development boards are limited, mainly based on SiFive P550 processors and T-head Xuantie C920 processors, with no host CPUs that meet the RVA23 architecture standards, nor corresponding AIA interrupt controllers, IOMMUs (Input/Output Memory Management Units), and hypervisors.Frans Sijstermans stated that once the RISC-V ecosystem matures, the standard CUDA version will support RISC-V architectures that comply with server platform specifications and Linux operating systems. In addition, in May of this year, NVIDIA launched NVLink Fusion technology, which deeply integrates NVIDIA’s high-speed interconnect technology NVLink with third-party ASICs, CPUs, and other heterogeneous chips to build semi-custom AI infrastructure. NVLink Fusion will provide rack-level solutions for customized RISC-V CPUs, enabling rapid deployment from RISC-V CPUs to complete data centers.Self-controllable and Inclusive: RISC-V Will Benefit the AI Industry“What technical advantages does RISC-V have in improving the performance and efficiency of generative AI algorithms?” During the roundtable discussion at the summit, attendees and the audience voted on this question. Ultimately, “open architecture facilitates hardware-software co-design,” “modular and scalable architecture,” and “simple and efficient instruction set” ranked in the top three.
Bao Yungang, Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, and Secretary-General of the RISC-V Alliance, believes that RISC-V can bring three advantages to AI. First, RISC-V can achieve better synergy with CPUs. The floating-point instructions of the 1980s and multimedia instructions of the 1990s have been integrated into CPUs. AI’s extended instructions will also be integrated into CPUs, providing advantages for agents to repeatedly call between multiple models. Second, RISC-V is flexible and customizable. Current AI inference scenarios are diverse, with cloud needing “full-blooded” large models, edge requiring “distilled” large models, and customization and fine-tuning based on specific needs. RISC-V allows developers to cut and optimize at the hardware level. Finally, currently, domestic AI chip companies have their own software stacks, presenting a “vertical silo” development model. RISC-V can provide a unified extended instruction set, integrating the software stack with upper-level compilers and libraries to co-build a software ecosystem on a global scale.Data shows that by 2030, the semiconductor market size will exceed one trillion dollars, with over 70% related to AI. Regarding the technical architecture of AI, Dai Weimin, Chairman of the Shanghai Open Processor Industry Innovation Center and Chairman of the China RISC-V Industry Alliance, made an analogy: training is the trunk, fine-tuning at the edge is the branches, and inference cards are the “leaves”; in the future, a large number of inference cards will be used on the edge. The advantages of RISC-V being “self-controllable and prosperous” will play a role in the AI era.Based on RISC-V, computing systems can achieve openness across a wider range of dimensions and more links in the industry chain. AI startup Tenstorrent, led by renowned chip technology expert Jim Keller as CEO, has established a full-stack solution based on RISC-V, from IP, chiplets, chips to boards/servers/systems. Its open chiplet architecture (OCA) realizes open-source at the physical layer, transport layer, protocol layer, system layer, and software layer. “Data shows that by 2028, 60% to 80% of high-performance AI will adopt chiplet architecture, and the benefits of chiplets include reducing R&D costs, improving availability, flexible combinations, and facilitating collaboration. Based on OCA, enterprises or research units can save R&D expenses and allocate more funds to enhance core value,” said Wei-Han Lien, Chief Architect of Tenstorrent.Currently, there are two mainstream architectures for AI chips: GPGPU and ASIC. Based on RISC-V, ASIC companies can adopt more flexible core configurations. In acceleration cards, Tenstorrent uses small cores known as “Baby RISC-V” to handle low-complexity but specialized tasks. For example, its Grayskull e75 acceleration card consists of 96 Tensix cores, each containing five programmable Baby RISC-V cores, with two RISC-V cores responsible for data movement and managing asynchronous read/write operations between external storage and local SRAM, while the remaining three cores are responsible for data unpacking, executing computation kernels, and data packing.While leveraging modular advantages, RISC-V’s openness ensures that various cores and architectures obtain a unified software interface to avoid ecological fragmentation. Meng Jianyi, CEO of Zhihui Computing and Chief Scientist at Alibaba DAMO Academy, stated, “Baby RISC-V” is a path for handling AI, significantly simplifying the control path of CPUs, concentrating limited silicon area on computing units, bringing business and computation closer together. However, to translate this into business, “Big RISC-V” needs to drive it. Additionally, computing matrix enhancements can also be integrated into RISC-V based on new devices and methods. Thanks to RISC-V’s openness, “Baby RISC-V,” “Big RISC-V,” or other physical devices can obtain unified interfaces and software programming interfaces, which will greatly benefit RISC-V’s innovation and ecological prosperity.Breaking Ecological Islands: RISC-V Accelerates Collaboration in the Automotive IndustryThe automotive sector, as a new type of edge intelligent terminal, has become a battleground for computing hardware and software manufacturers. In the rapidly evolving automotive electronic and electrical architecture, RISC-V has great potential.Hu Zhenbo, founder of Chipcome Technology, stated that traditional automobiles are relatively closed scenarios, with most established automotive chip companies adopting proprietary architectures, leading to fragmented automotive software ecosystems. As an internationally standardized instruction set architecture, RISC-V can connect isolated software development and establish a unified architecture. Moreover, RISC-V is an open standard, which will not create a dependency on a single IP supplier, which is the biggest prerequisite for RISC-V’s implementation in the automotive field. “Under this premise, leading automotive chip companies or neutral third-party IP companies can develop and form synergy within a large ecosystem,” Hu Zhenbo said.At the summit, reporters learned that domestic and foreign companies are closely engaged in R&D and adaptation work around automotive RISC-V, including IP, chips, and development boards in fields such as perception, connectivity, and domain control, adapting AUTOSAR software and development environments, as well as automotive RISC-V compilers and other tools. For example, Chipcome Technology has taken the lead in launching the RISC-V CPU IP—NA900, which is based on ISO26262 ASIL-B/D certification; Dongfeng Motor and China Information Technology jointly developed the domestically produced high-performance vehicle control chip DF30 and its AUTOSAR-compliant OS (operating system) and MCAL (Microcontroller Abstraction Layer), where DF30 is the industry’s first high-end automotive control chip based on a self-developed open-source RISC-V multi-core architecture, achieving a functional safety level of ASIL-D; Infineon announced in March this year that it will launch a new automotive MCU series based on RISC-V in the coming years, which will become part of Infineon’s automotive MCU brand AURIX.
At the summit exhibition area, Yiswei’s automotive MCU based on a 32-bit RISC-V CPUTo continue promoting RISC-V in automotive applications and leverage its open and modular advantages, the industry chain needs to increase collaboration.“At the IP delivery level, we need to enhance the stability, reliability, and security of RISC-V automotive-grade IP through technological empowerment and ecosystem co-construction, and improve its compatibility. At the chip design level, we should ensure the synergy between chip technology and applications through scenario-driven and standard empowerment. For Tier 1 suppliers, it is recommended to deeply integrate into the chip definition and development stages, improving applications through rapid iteration. For OEMs, we hope to prioritize opportunities for domestic RISC-V automotive chips by building demonstration projects to enhance market confidence and recognition, further promoting industry prosperity,” said Chen Yongzhou, CTO of Wuhan Binary Semiconductor.
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Further Reading:Shih Huikang, Deputy Director of the Electronic Information Department of the Ministry of Industry and Information Technology: Let RISC-V truly become a powerful engine for China’s technological innovationBao Yungang: If RISC-V is only used to replace ARM in situ, it will be “underutilized”Author丨Zhang XinyiEditor丨Qiu JiangyongArt Editor丨MariaSupervisor丨Zhao Chen
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