On July 18, 2025, during the second day of the 2025 RISC-V China Summit’s “High-Performance Computing Sub-Forum,” Liu Yanan, the chip technology director of China Mobile Cloud Capability Center, discussed the current implementation of RISC-V in the data center field from various aspects including industrial policy, advantages of RISC-V, and the current status and challenges of the RISC-V industry.
△ Liu Yanan, Chip Technology Director of China Mobile Cloud Capability Center
Policy Guidance Accelerates the Development of China’s RISC-V Industry
At the national level, due to the blockade of high-end chips from the West against China and the suppression of domestic high-end chip development, the state encourages technological innovation in the chip bottleneck field and the construction of a domestic chip ecosystem. At the local government level, there has been a shift from traditional simple financial subsidies to a systematic layout of the industrial chain, innovation chain, financial chain, and talent chain. At the enterprise level, China Mobile Group is continuously deepening its technological innovation strategy, playing a leading role as a central enterprise to drive joint innovation in the upstream and downstream of the chip industry chain.
Liu Yanan further pointed out that in April of this year, there were rumors that the Ministry of Industry and Information Technology led eight ministries to issue a document encouraging the nationwide promotion of RISC-V. China Mobile Chairman Yang Jie has also stated on various occasions that he supports the integration of software and hardware innovation. Of course, China Mobile’s technological innovation is more about leading and assisting everyone in the innovation of chip and software-hardware integration through industrial chain collaboration. At the local level, Beijing and Shanghai are particularly active, with Beijing having the Open Chip Institute and Shanghai having the Open Processor Industry Innovation Center.
Breaking the Monopoly of X86 and Arm, RISC-V Shows Obvious Cost-Performance Advantages
From an industrial analysis perspective, the cost of chips currently accounts for more than half of server costs and is monopolized by foreign chip giants. According to IDC data, in basic servers, the cost of CPU and GPU chips accounts for about 30%; in high-performance servers, the cost of CPU and GPU chips can reach 50%-83%. Among them, Intel and AMD’s x86 CPUs account for about 86% of the global server market, while NVIDIA, with its CUDA ecosystem barrier, has over 90% market share in global server GPUs.
Moreover, from the perspective of cloud vendors, general-purpose chips are increasingly unable to meet demand. Custom or self-developed chips can significantly improve cost performance, enhance energy efficiency, and build differentiated competitiveness.
According to Liu Yanan, the performance of the customized Intel 8378C can improve by single-digit percentages compared to the non-customized 8358P, while costs can be reduced by double-digit percentages. If using the Arm architecture-based ZTE Summit processor, the overall performance can improve by double-digit percentages compared to the customized Intel 8378C, and prices can also be reduced by double-digit percentages, showing significant cost-performance improvement. If RISC-V architecture server processors are adopted, they can bring about double-digit percentage cost reductions compared to the ZTE Summit.
Currently, many cloud giants such as Amazon, Google, Alibaba, Huawei, Baidu, Tencent, and Microsoft are customizing or self-developing chips and deploying them at scale to achieve deep cost reductions and establish differentiated competitiveness. “Cloud computing has entered a phase of elimination, and customized and self-developed chips will become core competitiveness,” Liu Yanan said.
So, why does China Mobile choose RISC-V? It is well known that X86 is a closed architecture dominated by Intel and AMD, and its instruction set is a “black box”; the Arm architecture is also dominated by Arm, belonging to a closed instruction set with a single authorized microarchitecture, only a few manufacturers are granted Armv8 instruction set authorization, and the costs are high, with subsequent instruction set upgrades requiring re-authorization; RISC-V, on the other hand, has a completely open instruction set and sufficient competition in microarchitecture.
Liu Yanan pointed out that the advantages of RISC-V can be summarized in three “openness”: open instruction set, open track, and open ecosystem. RISC-V aligns with future development trends and can create a closed-loop path from architecture to algorithm. Choosing RISC-V means being able to stand on one’s own, embrace openness, and accelerate collaborative innovation, with the potential to achieve a leap from “usable” and “easy to use” to “leading” for domestic processors in the future.
Regarding the current domestic server CPU manufacturers, there are mainly six, including Haiguang Information and Zhaoxin with C86 architecture, Huawei and Feiteng with Arm architecture, and Loongson and Shenwei with self-developed architectures. Liu Yanan revealed: “Among these six major companies, one may turn to RISC-V. At that time, the leader of this company said, ‘You RISC-V people are a bunch of rabble,’ but now the situation is completely different because all six have passed the national test. I particularly want to see which company that does RISC-V can pass the national test first, as this is a deployment for central enterprises and is a very important barometer, especially in the field of trusted computing.”
Entering the High-Performance Computing Market, RISC-V’s Shortcomings are Rapidly Being Addressed
Although RISC-V currently still has shortcomings in performance and an immature software ecosystem, with many leading manufacturers betting on and leading the way, talent is flooding in, and the fact that RISC-V’s ISA has no historical baggage is also allowing RISC-V CPU performance to gradually approach that of mainstream X86 and Arm CPUs, and the ecosystem is evolving rapidly, addressing these two shortcomings quickly.
For example, international RISC-V manufacturers represented by SiFive, Ventenna, and Tenstorrent are mainly laying out in high performance, Chiplet, and RISC-V DataFlow directions; while domestic RISC-V represented by the Open Chip Institute, Zhihe Computing, and Jinxuan Shikong are mainly focusing on industrial ecology, high performance, and IOMMU virtualization.
Liu Yanan pointed out that the single-core Specint 2006 score of processors needs to reach 15 points/GHz, which is the mainstream threshold for data center CPUs. RISC-V needs to break through this threshold and continuously improve performance to benchmark against mainstream data center CPUs to have a chance.
As the current photomask size has reached its limit, increasing chip area to enhance performance has been restricted, and the development of advanced process technology has also significantly slowed down, Chiplet has become a necessary option for large chips, making collaboration between foundries and advanced packaging particularly important. This also provides an opportunity for RISC-V architecture processors to catch up with mainstream architectures in performance.
Currently, many domestic RISC-V CPUs have already broken through the Specint 2006 score of 15 points/GHz, such as Alibaba’s Damo Academy Xuantie C930, which has reached 15.2 points/GHz, and the Open Chip Institute’s open-source RISC-V processor core “Kunming Lake V2,” which has also reached 15 points/GHz, and with compiler optimization, it can be improved to 18.5 points/GHz. This also means that domestic RISC-V CPUs now have the opportunity to compete directly with mainstream x86 and Arm CPUs.
“In addition to needing to achieve performance benchmarks against mainstream data center CPUs, RISC-V also needs to identify landing scenarios. Currently, general-purpose clusters carry user services, and migrating to RISC-V requires a process, while storage and intelligent computing are more backend clusters, where RISC-V is expected to break through first,” Liu Yanan explained: “In fact, data centers are also differentiated, and internal clusters are divided into front-end clusters and back-end clusters, with the front-end being general-purpose, while intelligent computing and storage are back-end clusters. Especially the intelligent computing cluster is quite special because it mainly runs PyTorch, TensorFlow, and operator libraries, and during runtime, it also needs to integrate communication. The variety of user software it carries is not as diverse as general-purpose computing, and it can combine more innovations with RISC-V.”
AI Software Stack is the Biggest Pain Point, RISC-V Can Foster Consensus
From the market perspective, IDC data shows that by 2027, the scale of China’s intelligent computing cloud, integrated machines, and edge-side chip markets will be 12.6 billion yuan, 46.8 billion yuan, and 28.3 billion yuan respectively. In this regard, Liu Yanan believes that RISC-V CPUs can first try to enter the integrated machine market while entering edge-side markets like AIPC, but in the future, the intelligent computing cloud market will become a new focus of competition, where inclusiveness and cost performance will become RISC-V’s breakthrough advantages.
From the perspective of intelligent computing chip architecture, there are currently mainly: mainstream general-purpose GPU/GPGPU architectures; DSA (domain-specific architecture) focusing on energy efficiency and customization, including NPU (such as Huawei Ascend, Cambricon), PE-level data flow (Tenstorrent), FU-level data flow (such as Google TPU), and dedicated ASICs. However, these types of chips have high programming difficulty and poor compatibility, making software the biggest pain point.
Liu Yanan explained that the AI software stack and CPU software stack are completely different. The AI software stack is heavy and chaotic, deeply bound to CUDA, and is still continuously penetrating. In contrast, the CPU software stack is simple and unified, achieving hardware-software decoupling through ISA. The current problem with the AI stack is siloed repetition and difficulties in cloudification, with chip manufacturers facing heavy burdens in evolution. Both GPU and DSA chip manufacturers need to independently build AI software stacks that interface with mainstream frameworks and models, and they need to do this for DL compilers and operator libraries, with all running drivers needing to be developed and maintained independently, which overall requires huge investment and is quite difficult to evolve.
For example, the team at Moore Threads has about 1,000 people, of which six to seven hundred are working on software. Similarly, why does NVIDIA say it is a software company? Because, in terms of personnel ratio, it is indeed a software company. And this kind of manpower expenditure is repetitive investment; everyone’s underlying technology is quite similar and needs to be done independently.
In contrast, if the AI software stack is built on the open RISC-V, it can maximize reuse, allowing chip manufacturers to focus on innovation and accelerate evolution. “So does RISC-V have advantages at the AI instruction set level? I believe it does not. What is RISC-V’s advantage? I think its biggest advantage is that it can foster consensus. Using RISC-V to make CPUs is the same; its biggest advantage is to foster consensus, and the repetitive underlying components can be universal. In addition, under the open RISC-V ecosystem and standard instruction set, hardware and software can achieve decoupling, allowing chip manufacturers to leverage the advantages of customizable instruction sets and architectures to focus on innovation,” Liu Yanan said.
Challenges Facing RISC-V
From the perspective of RISC-V’s AI roadmap, there are currently two main directions: RISC-V CPU + AI (IME/AME/AI accelerators) for matrix expansion, where the CPU still occupies more chip area; AI + RISC-V, where TPU/GPU integrates RISC-V internally. Liu Yanan believes that with the continuous development of RISC-V, it may ultimately evolve towards a fusion state of RISC-V = AI in the future.
Regarding the challenges RISC-V chips face in developing towards high computing power, Liu Yanan believes that the localization of the supply chain will become the biggest bottleneck and shortcoming in the short term. For example, in high-end processes, domestic advanced process yield is low, capacity is insufficient, and supporting facilities are not mature; the implementation of domestic advanced processes is limited, and IP and PDK optimization is insufficient; memory bandwidth (advanced HBM) is inadequate, restricting CPU intelligent computing expansion and GPU localization. We need to seize the opportunity for localization through architectural innovation, 2.5D, 3D advanced packaging, and heterogeneous integration to open up new paths for improving computing power.
“Although domestic RISC-V chip companies will face challenges in profitability, and our company also has challenges in achieving its KPIs, overall, the future is bright, and we will definitely succeed. The process will not be achieved overnight, especially in the data center field, where this cycle may be relatively long,” Liu Yanan anticipated.
Editor: Chip Intelligence – Lang Kejian
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