“Energy consumption”, “carbon emissions”, “range anxiety” – these issues in the semiconductor field are closely related to chip power consumption. Currently, we are in the midst of a digital wave, accompanied by the booming development of technologies such as the Internet of Things, mobile computing, autonomous vehicles, and data centers. Chip designers are facing a huge challenge: how to effectively manage power consumption while pursuing high performance? This is because high energy consumption not only leads to system overheating, shorter battery life, and increased costs but also raises carbon emissions, thereby having an adverse impact on the environment.
Achieving optimal performance per watt has become a “must-learn” for chip designers across various industries. Those who can solve the energy consumption problem more effectively may gain a competitive advantage.
Emerging Markets Facing Power Consumption Challenges
In recent years, emerging markets such as smart vehicles, data centers, and artificial intelligence (AI) have been rapidly developing, leading to an increasing demand for high-performance chips. AI accelerators, known for their TOPS performance, have gradually become the backbone of the semiconductor field, providing strong computing power support for these emerging areas. However, high computing power and high performance also mean high power consumption.
In the automotive sector, with the rapid development of vehicle electrification, intelligence, and connectivity, driving assistance systems, intelligent safety features, and advanced infotainment systems have become widespread across all price tiers, no longer exclusive to high-end brands. The core of these innovative features relies on silicon chip technology. Industry data shows that traditional internal combustion engine vehicles (ICE) contain over 1,000 chips, while this number doubles in electric vehicles (EV).
So many electronic devices mean consuming a large amount of electrical energy:
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For internal combustion engine vehicles, this increases the burden on the electrical and charging systems, prompting automakers to consider transitioning from the current 12V system to a 48V system. This can reduce the current levels in vehicle wiring, allowing for the use of cheaper, thinner wires while improving reliability.
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For EVs, the high energy consumption of onboard electronic devices directly relates to range, with “range anxiety” becoming the second most important consideration for consumers after price when purchasing a vehicle. Modern vehicles, especially those integrated with advanced driving assistance systems (ADAS), autonomous driving technology, and audio-visual intelligent features, need to process large amounts of data from multiple sources, such as video, audio, radar, and LiDAR. These data sources provide vehicles with detailed information about their surroundings, enabling safer and smarter driving. The more advanced the driving assistance and safety features, the higher the energy consumption, which in turn increases the frequency of EV charging and puts pressure on the power grid, adversely affecting the environment.
Data centers, as the core of digital infrastructure, face even more prominent energy consumption issues. With the development of cloud computing and big data, the scale of data centers continues to expand, and the demand for processing power keeps rising. Chips, as the “heart” of data centers, have become a significant burden in terms of energy costs that operators cannot ignore.
The rapid development of the artificial intelligence market has also brought energy consumption issues. AI algorithms typically require a large amount of computational resources, especially when training complex machine learning models. For example, ChatGPT requires computing resources that approximately double every 3-4 months, with parameters reaching the T-level. Training a single deep learning model like GPT-3 generates about 500 tons of carbon dioxide emissions, equivalent to a regular gasoline vehicle driving one million miles.
Recently, the U.S. Department of Energy (DoE) called for a 1000-fold increase in semiconductor energy efficiency. From the perspective of the semiconductor industry, this means reducing chip power consumption. Whether for AI training in data centers or inference at the edge, optimizing performance per watt is clearly the top priority for the semiconductor industry. Reducing energy consumption not only minimizes environmental impact but also lowers operating costs, maximizes performance within limited power budgets, and helps mitigate thermal challenges.
For markets such as data centers, automotive, and AI that have high computing power and energy consumption demands, optimizing power consumption is an inevitable path for development. In the long run, achieving a balance between technological innovation and environmental sustainability is key to driving the continuous and healthy development of these fields.
How to Shape the Future of Low-Power SoC Design?
When it comes to power consumption optimization methods for SoC chips, the design approaches have undergone significant technological evolution over the past few decades.
Initially, the semiconductor industry primarily relied on circuit simulators like SPICE (Simulation Program with Integrated Circuit Emphasis) to evaluate power consumption at the transistor level. Although SPICE had limitations in processing power and computation speed, it was one of the most advanced tools of its time. With technological advancements, SPICE gradually evolved into tools capable of performing higher-precision gate-level power consumption analysis, providing greater accuracy in simulating and analyzing electronic circuit energy consumption.
During the mid-stage of technology, the industry transitioned to more advanced gate-level tools based on specialized power characteristic libraries, achieving higher-level abstract simulations. This trend then extended to register transfer level (RTL), system-level methods, and even expanded into simulation power analysis. While this transition offered more opportunities to reduce power consumption at higher abstraction levels, it could sacrifice some analysis accuracy. When delving into specific design stages, such as RTL and implementation, the accuracy of power consumption analysis improves but may sacrifice design flexibility.
Today, to improve the accuracy of complex chip designs, the industry is increasingly focusing on RTL and higher levels of abstraction. This involves developing higher-level models for different components, such as IP blocks, processor cores, and hardware accelerators. Simulation technology plays an important role in this aspect, providing more realistic power consumption analysis, no longer relying solely on synthesized data vectors but using actual workloads for analysis.
Of course, chip design methods and requirements may vary for different application areas. For example, AI accelerators typically consist of arrays made up of thousands of processing elements (tiles). For designs exceeding one billion gates, advanced simulation systems need to run billions of cycles to reduce power consumption and leakage, providing multiple accurate iterations for multi-domain hardware and software power validation.
For energy-sensitive applications like electric vehicles, a comprehensive consideration of the entire vehicle system’s construction is required, making hardware architecture decisions a key step in the design process. When planning the entire automotive hardware system, engineers need to choose between different types of processors—such as general-purpose CPU architectures, dedicated digital signal processors (DSP), and hardware accelerators—to find a balance between flexibility, efficiency, and specialization. Additionally, the design of the memory subsystem should not be overlooked. To make these critical design decisions, architects need access to a system that can robustly model the power, performance, and area (PPA) characteristics of the hardware. This includes not only the physical attributes of the hardware but also the performance under different use cases.
It is evident that managing chip power consumption is a complex and critical task. Therefore, throughout the entire chip design cycle, designers must adopt a comprehensive low-power strategy, addressing every detail from the initial design phase to the final physical implementation phase to achieve optimal energy efficiency.
The journey to low power consumption for chips needs to be integrated throughout the chip’s lifecycle. First, during the RTL phase, power consumption optimization methods should be employed, including shutting down unnecessary power domains, adjusting voltage and processor frequency, and more intelligently controlling clock and data flows, even leveraging AI to achieve low-power design in the design phase. Then, verification engineers validate whether these low-power methods are effective, requiring comprehensive power management strategies, such as Unified Power Format (UPF), ensuring that all verification methods—whether static, formal, or simulation-based—correctly understand and implement these strategies. Finally, after completing RTL power analysis and reductions, physical implementations, such as synthesis and layout tools, can further optimize PPA.
The basic methodology has been established, but challenges remain: How to ensure maximum power optimization accuracy at all design stages? The key to addressing this challenge lies in constantly improving and upgrading tools and methodologies to ensure they meet the ever-changing energy consumption requirements.
Synopsys Low-Power SoC Solutions:
From Architecture to Power Consumption Verification, Full Process Support for Power Optimization
In response to the semiconductor industry’s growing demands for power reduction and energy efficiency improvement, Synopsys has launched a comprehensive end-to-end solution—Energy-Efficient SoCs—to help chip designers across various fields achieve or exceed ambitious performance and energy efficiency targets in a cost-effective manner while accelerating time to market. This solution covers the entire design process, from architecture to RTL design and verification, to simulation-driven power analysis, implementation, and ultimately power consumption verification.
The following diagram shows Synopsys’s full process for this low-power solution. In the initial stages of the chip design process, Synopsys Platform Architect can be used for architectural exploration and early performance-power trade-offs based on pre-RTL architectural models and software workloads.
Synopsys’s end-to-end low-power solution
The next stage, Synopsys ZeBu Empower, is used for power consumption simulation, capable of analyzing and exploring software workloads to identify key windows for further analysis and exploration. Silicon Valley-based AI chip startup SiMa.ai has begun using ZeBu Empower to design high-performance, low-power AI chips for smart edge applications to reduce power consumption. In terms of energy efficiency improvement, SiMa.ai has successfully increased the frame rate per watt per second (FPS) of its low-power MLSoC by 2.5 times. SiMa.ai’s silicon engineering director, Sounil Biswas, mentioned in a speech at the 2023 SNUG Silicon Valley Conference that the data from Synopsys ZeBu Empower is highly consistent with actual board measurement results.
To complement ZeBu Empower and achieve low-power RTL design, Synopsys also offers Synopsys PrimePower RTL, a tool for RTL power analysis and reduction that possesses timing-driven capabilities and considers physical design logic synthesis with integrated computing engines, consistently providing accurate power results (with power results differing from physical layout computations within ±15%). Synopsys PrimePower RTL can also conduct high-precision RTL power exploration as RTL matures.
Synopsys Fusion Compiler is a comprehensive and integrated RTL-to-GDSII implementation system that can achieve additional PPA optimization. Next, the verification engine of PrimePower and RedHawk (from Ansys, now part of Synopsys) merges to provide the fastest convergence speed and best result quality (QoR). Synopsys PrimePower is regarded as the gold standard for power verification solutions and has been certified by leading foundries worldwide, suitable for processes up to 3 nanometers, providing fast running performance and distributed processing to achieve high precision in the verification phase, with accuracy differing from SPICE and silicon measurement results by only a few percentage points.
Synopsys’s energy-efficient SoC development process focuses on finding and implementing opportunities to reduce power consumption at every stage of chip design, thereby creating high-energy-efficient chips. Its approach adjusts the balance of power consumption and performance based on the software running conditions in actual usage scenarios, avoiding unexpected issues during real-world use. Through early and accurate power analysis, chip engineers can quickly and effectively achieve their PPA targets.
Conclusion
In summary, managing power consumption in chip design is a complex and critical task. Low-power design methods have come a long way, evolving from basic tools to complex simulation solutions, continuously driving advancements in the chip industry. In this new era that emphasizes both high performance and high energy efficiency, Synopsys’s newly launched end-to-end energy-efficient SoC solution will undoubtedly become a key force in driving system-on-chip designs toward higher energy-saving goals.
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