Summary of Leakage Current Failure Analysis Cases for SOC Chips [Part A: Statement from the Analog Supervisor]

Hello everyone!Recently, during the testing of standby power consumption for the XXX project chip at our company, it was found that some chips were normal while others exhibited additional leakage current. The leakage current varied significantly between chips, ranging from a few microamperes to 200 microamperes. Moreover, there were some perplexing phenomena; for instance, when a finger touched any of the LCD multiplexing pins on the chips with leakage current, the standby power consumption would return to normal. Ultimately, after conducting a “thermal imaging analysis” at a relevant external institution, we identified the location of the leakage current and discovered that one of the LCD analog level signals, VBIAS_SEG03, was connected to a large Digital Buffer in the MCU. When the chip enters standby mode, this VBIAS_SEG03 node is left floating, resulting in a random voltage level, which causes leakage current at the input of the Digital Buffer. When the input of the Inverter is scanned from 0V to VDD (3V), the power consumption is exactly around 0uA to 200uA, corroborating the test results.Based on the above case analysis, I would like to share the following summary with everyone. I believe that many of you working on SOC projects may encounter similar issues, so please take heed.1. Current drawbacks in the SOC chip layout process at our companyWhen creating the top-level layout for SOC chips, the analog IC designers use Virtuoso to build the top-level circuit diagram, and then the digital IC designers write the top-level Verilog netlist based on the analog IC designers’ circuit diagram and provide it to the digital backend for layout.【Drawback 1: Risk of errors】.Here, a signal line that should have been analog (e.g., VBIAS_SEG03) is written into the top-level Verilog, turning it into a digital signal.【Drawback 2: “No distinction made”】.During digital auto-routing, these signals’ loads are evaluated, and if the drive is insufficient, buffers are inserted. The final LVS of the digital netlist is extracted from the auto-routed layout. This means that LVS is meaningless for digital modules, akin to using one’s own answers as the standard to grade one’s exam.【Drawback 3: “Self-deception”】.Ultimately, since the final layout differs significantly from the original top-level circuit diagram created by the analog IC designers, the simulation verification of the top-level circuit diagram by the analog IC designers can no longer prove whether the final silicon chip is correct.【Drawback 4: “Seemingly correct but actually incorrect”】.I remember when I took over the historical project YYY, I discussed the top-level layout issues with the digital layout and design personnel, and I was quite shocked by this process. However, after hearing the digital layout personnel’s descriptions, this process does have its advantages, as it simplifies many layout wiring tasks, especially since SOCs have many IO pins and numerous connections for each IO. Additionally, the number of connections for the analog-digital interface in SOCs is also quite large. Adopting the previous layout method, which primarily focused on analog circuits with digital modules as a supplement (where digital layout is a separate module placed into the analog layout and manually connected to the top-level circuit), would inevitably be very inefficient. Furthermore, some digital signals indeed require buffers to meet drive and timing requirements! Therefore, future SOC layouts may still use this digital-centric, analog-supplementary approach, but process optimization needs to be considered!I wonder if it is possible to specify in Verilog or during subsequent backend routing that certain analog signal lines should not have buffers inserted. For example, not calculating load and drive capability, or setting analog signal nodes to have infinite drive, etc.? This might help overcome drawbacks two, three, and four. If anyone has other ideas, please feel free to share them for discussion to improve the process!2. The following two points are suggestions on how to avoid the issue of inserting Digital Buffers into analog signal lines mentioned in the previous case under the current SOC chip layout process.

• For digital backend designers— Before using tools for automatic layout and routing, prioritize manual connections for nets with analog attributes. If there are many connections for these analog nets, making manual connections inconvenient, then after using tools for automatic layout and routing, each of these analog nets should be checked individually to ensure correct connections without any Digital Buffers or other digital units inserted.
• For analog frontend designers— When checking the layout, in addition to the checks listed in the integrated circuit review list, also focus on checking these automatically routed analog nets to ensure their connections are consistent with your designed top-level circuit, adding an extra layer of defense.

Do you think the analog supervisor’s statements are reasonable? Do you agree with his views?If you agree, please like and save this post.If you disagree, feel free to leave comments in the discussion section below!Since we are inserting digital BUF into analog signals during the digital layout phase, how will the layout supervisor explain this? Stay tuned for the next breakdown.