What is Embedded
IEEE (Institute of Electrical and Electronics Engineers) defines embedded systems as “devices used to control, monitor, or assist the operation of machines and equipment”. The original text is: Devices Used to Control, Monitor or Assist the Operation of Equipment, Machinery or Plants.
An embedded system is a specialized computer system that is part of a larger device or equipment. Typically, an embedded system is a control program stored in ROM within an embedded processor control board. In fact, all devices with digital interfaces, such as watches, microwaves, VCRs, cars, etc., use embedded systems, and some embedded systems also include operating systems, but most embedded systems implement the entire control logic with a single program.
Defined by its application objects, an embedded system is a combination of software and hardware, and can also encompass mechanical and other auxiliary devices. The widely accepted definition of embedded systems in China is: application-centered, based on computer technology, with customizable software and hardware, and specialized computer systems that meet the strict requirements of application systems regarding functionality, reliability, cost, size, and power consumption.
An embedded system device generally consists of an embedded computer system and an execution device. The embedded computer system is the core of the entire embedded system, consisting of hardware layer, middleware layer, system software layer, and application software layer. The execution device, also known as the controlled object, can accept control commands issued by the embedded computer system and perform the specified operations or tasks. The execution device can be simple, like a tiny motor in a mobile phone that activates when the phone is in vibration mode; or complex, like the SONY Aibo robotic dog, which integrates multiple tiny control motors and various sensors to perform various complex actions and perceive various state information.
Composition of Embedded Systems
1. Hardware Layer
The hardware layer includes embedded microprocessors, memory (SDRAM, ROM, Flash, etc.), general device interfaces, and I/O interfaces (A/D, D/A, I/O, etc.). By adding power circuits, clock circuits, and memory circuits to an embedded processor, an embedded core control module is formed. Both the operating system and application programs can be solidified in ROM.
2. Middleware Layer
The layer between the hardware and software layers is the middleware layer, also known as the Hardware Abstract Layer (HAL) or Board Support Package (BSP). It separates the upper software from the lower hardware, making the system’s lower driver programs independent of the hardware, allowing upper layer software developers to develop without worrying about the specific conditions of the lower layer hardware, using the interfaces provided by the BSP layer. This layer generally includes initialization of the relevant lower hardware, input/output data operations, and hardware device configuration functions. In fact, the BSP is a software level that lies between the operating system and the lower hardware, including most of the software modules closely related to hardware in the system. Designing a complete BSP requires completing two parts of work: the BSP function for hardware initialization of the embedded system, and designing hardware-related device drivers.
3. System Software Layer
The system software layer consists of a real-time multitasking operating system (RTOS), file system, graphical user interface (GUI), network system, and general component modules. RTOS is the foundation and development platform for embedded application software.
Real-Time Systems
(1) Definition: A system that can complete its functions within a specified time and respond to external or internal events, synchronously or asynchronously.
(2) Difference: General systems generally pursue average response time and user convenience; real-time systems mainly consider system behavior under worst-case scenarios.
(3) Characteristics: Time constraints, predictability, reliability, and interaction with the external environment.
(4) Hard Real-Time (Strong Real-Time): Refers to applications where the time requirements must be fully met; otherwise, it may cause major safety incidents, significant loss of life and property, and ecological damage, such as in aerospace and military applications.
(5) Soft Real-Time (Weak Real-Time): Refers to applications that have time requirements, but occasional violations of these requirements do not severely impact system operation or the environment, such as monitoring systems and real-time information acquisition systems.
(6) Task constraints include: time constraints, resource constraints, execution order constraints, and performance constraints.
Real-Time System Scheduling
(1) Scheduling: The entire process of determining when and where each task in a set of real-time tasks and system resources is executed.
(2) Preemptive Scheduling: Typically priority-driven scheduling, such as uCOS. The advantage is good real-time performance and fast response; the scheduling algorithm is relatively simple and can guarantee the time constraints of high-priority tasks; the disadvantage is that there are many context switches.
(3) Non-Preemptive Scheduling: Typically time-slice allocated scheduling, which does not allow tasks to be interrupted during execution. Once a task occupies the processor, it must finish executing or voluntarily release it, such as in WinCE. The advantage is fewer context switches; the disadvantage is low effective resource utilization of the processor and poor schedulability.
(4) Static Table Driven Strategy: The system generates a runtime schedule based on the time constraints and relationships of each task before running, indicating the start time and running time of each task.
(5) Priority Driven Strategy: Determines the execution order of tasks based on their priority levels.
(6) Classification of Real-Time Tasks: Periodic tasks, sporadic tasks, and aperiodic tasks.
(7) General Structural Model of Real-Time Systems: Data acquisition tasks implement the collection of sensor data, data processing tasks process the collected data and send the processed data to the actuator management tasks for control.
Embedded Microprocessor Architecture
(1) Von Neumann Architecture: Programs and data share the same storage space, with program instruction storage addresses and data storage addresses pointing to different physical locations in the same memory, using a single address and data bus, with the same width for programs and data. Examples: 8086, ARM7, MIPS…
(2) Harvard Architecture: Programs and data are stored in two independent memory spaces, with each memory independently addressed and accessed, separating program storage and data storage. For example: AVR, ARM9, ARM10…
(3) Comparison of CISC and RISC Characteristics.
The time P required for a computer to execute a program can be calculated using the following formula:
P=I×CPI×T
I: The number of instructions executed by the high-level language program when compiled to run on the machine.
CPI: The average number of cycles required to execute each instruction.
T: The time for each machine cycle.
(4) The Idea of Pipelining: In the CPU, transform the serial execution process of an instruction into overlapping execution of several instruction subprocesses within the CPU.
(5) Indicators of Pipelining:
Throughput: The number of results processed by the pipeline in a unit of time. If the subprocesses of the pipeline take different lengths of time, the throughput should be the reciprocal of the longest subprocess.
Establishment Time: The time from when the pipeline starts working to when it reaches maximum throughput. If m subprocesses take the same time, t, then the establishment time T=mt.
(6) Byte Order of Information Storage
A. Memory unit: byte (8 bits)
B. Word length determines the addressing capability of the microprocessor, i.e., the size of the virtual address space.
C. The virtual address space of a 32-bit microprocessor is 2^32, i.e., 4GB.
D. Little-endian byte order: the low byte is at the low address in memory, and the high byte is at the high address in memory.
E. Big-endian byte order: the high byte is at the low address in memory, and the low byte is at the high address in memory.
F. The storage order of network devices depends on the data link layer in the OSI model.
Basic Logic Circuits
(1) Based on whether the circuit has storage functionality, logic circuits can be divided into: combinational logic circuits and sequential logic circuits.
(2) Combinational Logic Circuits: The output of the circuit at any moment depends only on the input signals at that moment and is independent of the previous state of the circuit. Common logic circuits include decoders and multiplexers.
(3) Sequential Logic Circuits: The output of the circuit at any moment depends not only on the input at that moment but also on the state of the circuit at that moment. Therefore, sequential circuits must include memory elements. Flip-flops are the basic components of sequential logic circuits. Common sequential logic circuits include registers and counters.
(4) Truth tables, Boolean algebra, De Morgan’s laws, and the concept of gate circuits.
(5) NOR (not-or) and NAND (not-and) gate circuits are called universal gate circuits, capable of implementing any logical function.
(6) Decoder: A combinational logic network with multiple inputs and outputs. For each n-bit binary code input, at most one output among m outputs is valid. When m=2^n, it is a full decoder; when m < 2^n, it is a partial decoder.
(7) Due to the low output current of integrated circuits at high levels and relatively high output current at low levels, when directly driving LEDs with integrated gate circuits, low-level drive methods are often used. The liquid crystal seven-segment display (LCD) utilizes the different optical characteristics of liquid crystals with and without an external electric field to display characters.
(8) Clock signals are fundamental to sequential logic, used to determine the appropriate update of states in logic units. Synchronization is the primary constraint in clock-controlled systems.
(9) When selecting flip-flops, the triggering method is a crucial factor. There are two triggering methods:
Method 1: Level-triggered method: has a simple structure and is commonly used to form temporary storage registers.
Method 2: Edge-triggered method: has strong resistance to data line interference and is commonly used to form registers, counters, etc.
Bus Circuits and Signal Driving
(1) A bus is a collection of various signal lines, serving as a common pathway for transmitting data, addresses, and control information between parts of an embedded system. At any given moment, each pathway can transmit one binary signal. Depending on the type of information transmitted by the bus, it can be divided into: data bus (DB), address bus (AB), and control bus (CB).
(2) Main parameters of the bus:
Bus Bandwidth: The amount of data that can be transmitted on the bus within a certain time, generally expressed in MByte/s.
Bus Width: The number of bits (bit) that the bus can transmit simultaneously, commonly referred to as the concept of bus width, such as 32-bit or 64-bit. The wider the bus width, the greater the data transfer rate per second, which means the bus bandwidth is wider.
Bus Frequency: The working clock frequency measured in MHz. The higher the working frequency, the faster the bus speed, which means the bus bandwidth is wider.
Bus Bandwidth = Bus Width × Bus Frequency / 8, unit is MBps.
Common Buses: ISA bus, PCI bus, IIC bus, SPI bus, PC104 bus, and CAN bus, etc.
(3) Only devices with tri-state outputs can be connected to the data bus; commonly used tri-state gates are output buffers.
(4) When the load connected to the bus exceeds its load capacity, a buffer or driver must be added between the bus and the load; the most commonly used is the tri-state buffer, which serves to drive and isolate.
(5) Using bus multiplexing technology can achieve sharing of data and address buses. However, it brings two problems:
A. It is necessary to add external circuits to multiplex and decouple the bus signals, such as address latches.
B. The bus speed is relatively lower than that of non-multiplexed bus systems.
(6) Two types of bus communication protocols: synchronous mode and asynchronous mode.
(7) Solving the bus arbitration problem is based on the concept of priority (priority).
Level Conversion Circuits
(1) Digital integrated circuits can be divided into two major categories: bipolar integrated circuits (TTL) and metal-oxide-semiconductor (MOS).
(2) CMOS circuits are widely used due to their low static power consumption, high operating speed, and strong anti-interference capability.
(3) The way to solve the interface difficulties between TTL and CMOS circuits is to connect a pull-up resistor R between the output end of the TTL circuit and the power supply. The value of pull-up resistor R is determined by the leakage current IOH of the TTL high-level output. Different series of TTL should use different R values.
Basic Information Representation and Operations in Embedded Systems
(1) Carry Counting System and Conversion: This is relatively simple, and one should master how to perform conversions, as it may be a potential exam question.
(2) Representation of Numbers in Computers: Source code, inverse code, and complement code.
The inverse code of a positive number is the same as its source code, and the inverse code of a negative number is obtained by inverting all bits of the source code except the sign bit.
The complement code of a positive number is the same as its source code, and the complement code of a negative number is obtained by adding one to its inverse code.
For example, the source code of -98 is: 11100010B
The inverse code: 10011101B
The complement code: 10011110B
(3) Fixed-point representation: The position of the decimal point is artificially set to remain fixed and unchanged.
Floating-point representation: The position of the decimal point is variable, composed of the mantissa and exponent parts.
Any binary N can be expressed as: N=2^P×S. S is the mantissa, P is the exponent.
(4) Chinese character representation: Understand the transformation between GB2318-80 Chinese standard code and internal code.
(5) Waveform quantization parameters in speech coding (simple calculation questions may arise)
Sampling frequency: The number of samples taken in one second, reflecting the size of the interval between sampling points.
The upper limit of human hearing is 20kHz, so a sampling frequency above 40kHz is sufficient to satisfy human needs.
The sampling frequency used in CDs is 44.1kHz.
Measurement accuracy: The quantization levels of the samples, with the current standard sampling levels being 8 bits and 16 bits.
Number of channels: mono and stereo. Stereo requires double the storage space.
Error Control Coding
(1) Based on the functionality of the code group, it can be divided into error detection codes and error correction codes. Error detection codes are those that can automatically detect errors, such as parity check codes; error correction codes are those that can not only detect errors but also automatically correct them, such as cyclic redundancy check codes.
(2) Parity check codes, Hamming codes, cyclic redundancy check codes (CRC).
Measurement Items of Error Control Coding in Embedded Systems
(1) Performance Indicators:
Divided into component performance indicators and comprehensive performance indicators, mainly including: throughput, real-time performance, and various utilization rates.
(2) Reliability and Safety:
Reliability is the most important and prominent basic requirement for embedded systems, ensuring that an embedded system can operate normally, generally measured by the Mean Time Between Failures (MTBF).
(3) Maintainability:
Generally represented by the Mean Time To Repair (MTTR).
(4) Availability
(5) Power Consumption
(6) Environmental Adaptability
(7) Versatility
(8) Security
(9) Confidentiality
(10) Scalability
The price in cost-performance ratio should include not only the direct purchase price of the embedded system but also installation costs, several years of operational maintenance costs, and software rental fees.
Evaluation Methods for Embedded Systems: Measurement Method and Model Method
(1) The measurement method is the most direct and basic method, requiring the resolution of two issues:
A. Determine the system parameters to be measured according to the research purpose.
B. Choose the tools and methods for measurement.
(2) There are two types of measurement methods: sampling method and event tracking method.
(3) The model method is divided into analytical modeling and simulation modeling. Analytical modeling uses mathematical equations to describe the system model, while simulation modeling uses the operation of simulation programs to dynamically express the state of embedded systems and perform statistical analysis to derive performance indicators.
(4) The most commonly used analytical model is the queuing model, which consists of three parts: input flow, queuing rules, and service agency.
(5) Evaluating the system using models requires addressing three issues: designing the model, solving the model, and calibrating and validating the model.
Interface Technology
1. Flash Memory
(1) Flash memory is a type of non-volatile memory that can be divided into NOR Flash and NAND Flash based on its structure.
(2) Characteristics of Flash Memory:
A. Block structure: Physically divided into several blocks, which are independent of each other.
B. Erase before write: The write operation of Flash can only change data bits from 1 to 0, not from 0 to 1. Therefore, before writing to memory, an erase operation must be executed to initialize the pre-written data bits to 1. The minimum unit of the erase operation is a block, not a single byte.
C. Operation instructions: To execute a write operation, a series of special instructions (NOR Flash) or a sequence of timing (NAND Flash) must be input to write data.
D. Bit inversion: Due to the inherent characteristics of Flash, a bit or several bits of data errors may occasionally occur during reading and writing. Bit inversion is unavoidable and can only be processed afterward through other means.
E. Bad blocks: Once a block is damaged, it cannot be repaired. The results of operations on damaged blocks are unpredictable.
(3) Characteristics of NOR Flash:
Application programs can run directly in Flash memory without needing to load code into system RAM. NOR Flash has high transmission efficiency, with high cost-effectiveness at small capacities of 1MB to 4MB, but its low write and erase speeds greatly affect its performance.
(4) Characteristics of NAND Flash
It can achieve very high storage density and has fast write and erase speeds, which is why all USB drives use NAND Flash as the storage medium. The challenge of using NAND Flash is that it requires a special system interface.
(5) Differences between NOR Flash and NAND Flash:
A. NOR Flash has a slightly faster read speed than NAND Flash.
B. The erase and write speeds of NAND Flash are much faster than those of NOR Flash.
C. NAND Flash has poor random read capabilities, suitable for continuous reading of large amounts of data.
D. NOR Flash has an SRAM interface that allows sufficient addressing to easily access each byte inside. NAND Flash shares an 8-bit bus for address, data, and commands (some products use 16 bits), requiring complex I/O interfaces for serial access during each read and write.
E. The capacity of NOR Flash is generally smaller, usually between 1MB and 8MB; NAND Flash is only used in products over 8MB. Therefore, NOR Flash is used in code storage media, while NAND Flash is suitable for data storage.
F. The maximum number of erase/write cycles for NAND Flash is one million times, while for NOR Flash, it is one hundred thousand times.
G. NOR Flash can connect like other memories and can run code directly on it; NAND Flash requires a special I/O interface and must first write a driver before executing other operations. Because designers must never write to bad blocks, this means that NAND Flash must always perform virtual mapping.
H. NOR Flash is used in fields requiring high data reliability, such as code storage, communication products, and network processing; NAND Flash is used in fields requiring high storage capacity, such as MP3 players, storage cards, USB drives, etc.
2. RAM Memory
(1) Characteristics of SRAM:
SRAM stands for Static Random Access Memory. As long as it is powered, it retains a value without a refresh cycle, composed of flip-flops as basic units, with low integration, where each SRAM storage unit comprises six transistors, making it more expensive. It has a high speed and is commonly used in high-speed cache memory.
Typically, SRAM has four pins:
CE: Chip select signal, active low.
R/W: Read/write control signal.
ADDRESS: A set of address lines.
DATA: A set of bidirectional signal lines for data transmission.
(2) Characteristics of DRAM:
DRAM stands for Dynamic Random Access Memory. It is a semiconductor memory that stores data in the form of charge. Each storage unit consists of a transistor and a capacitor, with data stored in the capacitor. The capacitor loses charge due to leakage, making DRAM devices unstable. It must be refreshed regularly to retain data.
The interface of DRAM is relatively complex, typically having the following pins:
CE: Chip select signal, active low.
R/W: Read/write control signal.
RAS: Row address select signal, usually connected to the high part of the address.
CAS: Column address select signal, usually connected to the low part of the address.
ADDRESS: A set of address lines.
DATA: A set of bidirectional signal lines for data transmission.
(3) Characteristics of SDRAM:
SDRAM stands for Synchronous Dynamic Random Access Memory. Synchronous means that memory operations require a synchronized clock, with internal command sending and data transmission based on it; dynamic means that the memory array requires continuous refreshing to prevent data loss. It typically operates at a main frequency of 133MHz.
(4) Characteristics of DDRAM:
DDRAM stands for Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR. DDRAM is based on SDRAM technology, where SDRAM transmits data once per clock cycle; DDR memory transmits data twice per clock cycle, once on the rising edge and once on the falling edge of the clock. At a main frequency of 133MHz, DDR memory can achieve a bandwidth of 133×64b/8×2=2.1GB/s.
3. Hard Disk, Optical Disk, CF Card, SD Card
4. GPIO Principles and Structure
GPIO is the most basic form of I/O, consisting of a set of input or output pins. Some GPIO pins can be programmed to change their working direction, usually having two control registers: data register and data direction register. The data direction register sets the direction of the port. If the pin is set to output, the data register controls the state of that pin. If the pin is set to input, the state of this input pin is controlled by the logic circuit layer on it.
5. A/D Interface
(1) The A/D converter is a circuit that converts analog electrical signals into digital signals. There are many methods to achieve A/D conversion, commonly used methods include counting method, dual integration method, and successive approximation method.
(2) Counting A/D Conversion Method
The main components of the circuit include: comparator, counter, D/A converter, and standard voltage source.
The working principle is simply that there is a counter that starts counting from 0, incrementing by 1 each time. Each increment value serves as input for the D/A converter, which generates a comparison voltage VO to compare with the input analog voltage VIN. If VO is less than VIN, the counter continues to count up by 1 until VO exceeds VIN, at which point the accumulated count value of the counter is the output value of the A/D converter.
This conversion method is simple but relatively slow, especially when the input analog voltage is high. For example, for an 8-bit A/D converter, if the input analog value is at maximum, the counter must count from 0 to 255, performing 255 D/A conversions and voltage comparisons to complete the conversion.
(3) Dual Integration A/D Conversion Method
The main components of the circuit include: integrator, comparator, counter, and standard voltage source.
The working principle is that the circuit first integrates the input voltage to be measured over a fixed time, then performs a reverse integration with a standard voltage at a fixed slope. The time taken for the reverse integration to return to its starting value is proportional to the input analog voltage value; the larger the input analog voltage, the longer it takes to return. By using a standard high-frequency clock pulse to measure the time spent on reverse integration, one can obtain the corresponding digital quantity for the input analog voltage, thus completing the A/D conversion.
This method has strong anti-interference capability for industrial frequency, high conversion accuracy, but slow conversion speeds, typically below 10Hz, mainly used in digital testing instruments, temperature measuring instruments, etc.
(4) Successive Approximation A/D Conversion Method
The main components of the circuit include: comparator, D/A converter, successive approximation register, and reference voltage source.
The working principle is essentially a binary search method, similar to the use of a balance scale. When performing A/D conversion, the D/A converter increases the conversion bits from high to low sequentially, generating different output voltages to compare with the input voltage. First, the highest bit is set to 1, comparing it with half of the reference voltage. If the input voltage is less than half of the reference voltage, the highest bit is set to 0; otherwise, it remains 1. Next, the next highest bit is set to 1, performing another binary search within the range of half, and so on, approaching the value step by step.
This method is fast and has high conversion accuracy, requiring only M clock pulses to complete the conversion for an N-bit A/D converter. It is commonly used for measuring transitions occurring over tens to hundreds of microseconds and is currently the most widely used conversion method.
(5) Important Indicators of A/D Conversion (some simple calculations may be asked)
A. Resolution: Reflects the A/D converter’s ability to respond to small changes in input, typically represented by the voltage level corresponding to the least significant bit (LSB) of digital output. An n-bit A/D converter can reflect 1/2^n of the full-scale analog input level.
B. Range: The range of analog input voltages that can be converted, divided into unipolar and bipolar types.
C. Conversion Time: The time required to complete one A/D conversion, the reciprocal of which is the conversion rate.
D. Accuracy: Accuracy and resolution are two different concepts; even with high resolution, accuracy may not be high due to temperature drift, linearity, etc. Accuracy can be represented in two ways: absolute accuracy and relative accuracy. Absolute accuracy is represented by the fraction of the least significant bit (LSB) of the digital quantity; relative accuracy is expressed as a percentage of the full-scale analog voltage.
For example, with a full-scale of 10V and a 10-bit A/D chip, if the absolute accuracy is ±1/2 LSB, the minimum effective unit of LSB is: 10/1024=9.77mV, the absolute accuracy is 9.77mV/2=4.88mV, and the relative accuracy is: 0.048%.
6. Basic D/A Interface
(1) D/A converters convert digital quantities into analog quantities.
(2) In integrated circuits, a T-type network is usually used to convert a digital quantity into an analog current, which is then converted to an analog voltage by an operational amplifier. D/A conversion actually requires these two steps.
(3) Classification of D/A Converters:
A. Voltage output type: commonly used as high-speed D/A converters.
B. Current output type: usually used with external operational amplifiers.
C. Multiplying type: can be used as modulators and to attenuate input signals digitally.
(4) Main indicators of D/A converters: resolution, settling time, linearity, conversion accuracy, temperature coefficient.
7. Keyboard Interface
(1) Two forms of keyboards: linear keyboards and matrix keyboards.
(2) There are two main methods for recognizing closed keys on a keyboard: row scanning method and row inversion method.
(3) The row scanning method is a commonly used recognition method for matrix keyboards, which proceeds in two steps:
A. Identify which column’s key is pressed: set all row lines to low, checking whether any column lines are low; if a column line is low, it indicates that a key in that column is pressed; otherwise, no key is pressed.
B. If a column has a pressed key, identify which row is pressed: set each row to low sequentially while keeping the others high, checking for changes in column lines; if a column line changes to low, it indicates that the key at the intersection of that row and column is pressed.
8. Display Interface
(1) The basic principle of LCD is to control the passage of light by supplying power to different liquid crystal units, achieving the purpose of display.
(2) There are two ways to provide light sources for LCD: projection type and reflection type. The LCD display of laptops is projection type, with a light source behind the screen, so external light sources are not needed. Generally, LCDs used on microcontrollers are reflection type, requiring external light sources to work. Electroluminescent (EL) is one way to provide light sources for LCD screens.
(3) Common LCDs can be classified into three types based on their driving methods: Twisted Nematic (TN), Super Twisted Nematic (STN), and Thin Film Transistor (TFT).
(4) LCDs available on the market come in two types: LCD display modules with driving circuits, which only require bus-type driving; and LCD displays without driving circuits, which use controller scanning methods.
(5) Typically, when the LCD controller works, it requests the bus through DMA and directly reads data from SDRAM at a specified address (display buffer), which is then converted into the scanning data format for the LCD display.
(6) The VGA interface is essentially an analog interface, generally using a unified 15-pin interface, including 2 NC signals, 3 display data lines, 5 GND signals, 3 RGB color components, 1 horizontal sync signal, and 1 vertical sync signal. The voltage standard for the color components is defined by the EIA as the RS343 standard.
9. Touch Screen Interface
(1) Based on working principles, touch screens can be divided into: surface acoustic wave screens, capacitive screens, resistive screens, and infrared screens.
(2) Touch screen control uses specialized chips, such as ADS7843.
10. Audio Interface
(1) Basic principle: Data input from the microphone is decoded by an audio codec to complete A/D conversion; the decoded audio data is sent to DSP or CPU for processing via the audio controller, and then sent to the audio encoder for D/A conversion before being output by the speaker.
(2) There are various formats for digital audio, with the three most common being:
A. Digital audio (PCM): The data format used by CDs or DVDs, with a sampling frequency of 44.1kHz. At 16-bit precision, the PCM audio data rate is 1.41Mb/s; at 32-bit precision, it is 2.42 Mb/s. A 700MB CD can store about 60 minutes of 16-bit PCM data format music.
B. MPEG Layer 3 audio (MP3): The audio format used by MP3 players. Stereo MP3 data rates range from 112kb/s to 128kb/s.
C. ATSC digital audio compression standard (AC3): The digital audio encoding standard for digital TV, HDTV, and movies, with stereo AC3 encoded data rates of 192kb/s.
(3) IIS is a commonly used serial audio digital interface for encoding or decoding audio data. The IIS bus only handles audio data, while other control signals need to be transmitted separately. IIS uses three serial buses: data line SD, field select line WS, and clock signal line SCK.
(4) When the data field width of the sender and receiver differs, the sender does not consider the receiver’s data field width. If the data field sent by the sender is smaller than the system field width, it fills low bits with 0; if the sender’s data width exceeds the receiver’s width, the excess bits beyond the LSB are truncated. The field select WS is used to select the left or right channel, with WS=0 indicating the left channel and WS=1 indicating the right channel. Additionally, WS allows the receiving device to store the previous byte and prepare to receive the next byte.
11. Serial Interface
(1) Serial communication refers to the transmission of data one bit at a time. Compared to parallel communication, serial communication has the advantages of fewer transmission lines and lower costs, making it particularly suitable for long-distance transmission; however, it is slower.
(2) There are three basic communication modes for serial data transmission: simplex, half-duplex, and full-duplex.
(3) In terms of information format, serial communication can be divided into two types: synchronous communication and asynchronous communication.
A. Asynchronous transmission: Each character is treated as independent information transmitted in a fixed and predetermined timing, but the timing between characters is arbitrary. In asynchronous communication, characters are transmitted frame by frame, with each frame synchronized by a start bit. The time intervals between each frame of data are fixed, while the time intervals between adjacent frames are variable.
B. Synchronous transmission: In synchronous mode, not only are characters synchronized between each other, but the timing between characters is also synchronized, meaning that many characters are grouped into one character block, and 1-2 synchronization characters are added before each block of information, along with appropriate error detection data.
(4) Asynchronous communication must adhere to three regulations:
A. Character format: start bit + data + parity bit + stop bit (the parity bit may be omitted), with the low bit transmitted first.
B. Baud rate: the number of bits transmitted per second.
C. Parity bit: odd/even check.
a. Odd check: the parity bit must ensure an odd number of “1s” in the character.
b. Even check: the parity bit must ensure an even number of “1s” in the character.
(5) The electrical characteristics of RS-232C: negative logic.
A. On TxD and RxD: logic 1 is -3V to -15V, logic 0 is 3V to 15V.
B. On control lines such as TES, CTS, DTR, DCD, etc.: signal active (ON state) is 3V to 15V; signal inactive (OFF state) is -3V to -15V.
(6) The level conversion between TTL standard and RS-232C standard uses integrated chip RS232.
(7) RS-422 Serial Communication Interface
A. RS-422 is a unidirectional, balanced transmission specification for single machine sending and multiple machine receiving, with a transmission rate of up to 10Mb/s.
B. RS-422 uses differential transmission, also known as balanced transmission, using a pair of twisted wires.
C. RS-422 requires a termination resistor, with a value approximately equal to the characteristic impedance of the transmission cable.
(8) RS-485 Serial Bus Interface
A. RS-485 is a standard built on the foundation of RS-422, adding multipoint and bidirectional communication capabilities, with communication distances ranging from several dozen meters to thousands of meters.
B. RS-485 transceivers use balanced transmission and differential reception, with the ability to suppress common-mode interference.
C. RS-485 requires two termination resistors. For short distances (under 300m), termination resistors may not be necessary.
12. Parallel Interface
(1) The data transmission rate of parallel interfaces is 8 times faster than that of serial interfaces, with a standard parallel interface data transmission rate of 1Mb/s, generally used to connect printers, scanners, etc., hence also known as the printer port.
(2) Parallel interfaces can be divided into SPP (standard parallel port), EPP (enhanced parallel port), and ECP (extended parallel port).
(3) Parallel buses are divided into standard and non-standard categories. Common standard parallel buses include IEEE 488 bus and ANSI SCSI bus. MXI bus is a high-performance non-standard universal multi-user parallel bus.
13. PCI Interface
(1) The PCI bus is a high-performance 32-bit and 64-bit bus that multiplexes addresses and data, serving as the interconnection mechanism between microprocessors and peripheral control components, and peripheral add-on boards.
(2) In terms of data width, PCI defines a 32-bit data bus, extendable to 64 bits. In terms of bus speed, there are two types: 33MHz and 66MHz.
(3) Compared to the ISA bus, the PCI bus multiplexes the address bus and data bus, supporting plug-and-play and interrupt sharing functionalities.
14. USB Interface
(1) The main features of the USB bus:
A. Simple to use, plug and play.
B. Each USB system has a host, and a maximum of 127 devices can be connected in this USB network.
C. Wide application range, supporting multiple devices to operate simultaneously.
D. Low-cost cables and connectors, using a unified 4-pin plug.
E. Strong error correction capabilities.
F. Lower protocol overhead leads to high bus performance, suitable for developing low-cost peripherals.
G. Supports multiple data streams and multiple message streams between the host and devices, and supports both synchronous and asynchronous transmission types.
H. Bus-powered, providing devices with 5V/100mA power supply.
(2) The USB system is described in three parts: USB host, USB device, and USB interconnection.
(3) The data transmission rates supported by the USB bus include three types: high-speed signaling rate of 480Mb/s; full-speed signaling rate of 12Mb/s; low-speed signaling rate of 1.5Mb/s.
(4) The USB bus cable has four wires: a pair of twisted signal lines and a pair of power lines.
(5) USB is a polling bus, where the main controller initiates all data transmissions. The peripherals connected to the USB share the USB bandwidth through a token-based protocol scheduled by the host.
(6) Most bus transactions involve the transmission of three packets:
A. Token packet: indicates what transaction is to be executed on the bus, the USB device to be addressed, and the direction of data transfer.
B. Data packet: transmits data or indicates that there is no data to transmit.
C. Handshake packet: indicates whether the transmission was successful.
(7) The USB data transmission model between the host and device endpoints is called a pipeline. There are two types of pipelines: stream and message. Message data has a structure defined by USB, while stream data does not.
(8) The transaction scheduling table allows flow control for certain stream pipelines, adjusting the data transmission rate at the hardware level by using NAK (negative acknowledgment) handshake signals to prevent buffer overflows or underflows.
(9) The most notable feature of USB devices is plug and play.
(10) Working principle: When a USB device is plugged into a USB endpoint, the host communicates with the device’s endpoint 0 through the default address 0. In this process, the host issues a series of standard requests to obtain descriptors, through which the host gathers all relevant device information, learning about the device’s status and how to communicate with it. The host then issues a Set Address request to assign a unique address to the device. Afterward, the host communicates with the device using the assigned address instead of the default address 0.
15. SPI Interface
(1) SPI is a synchronous protocol interface, with all transmissions referencing a common clock generated by the host, which the receiving devices use to synchronize the reception of the serial bit stream.
(2) When multiple devices are connected to the same SPI interface, the host selects the device using the chip select pin of the slave device.
(3) SPI primarily uses four signals: Master Out/Slave In (MOSI), Master In/Slave Out (MISO), Serial Clock (SCLK), and Slave Select (CS).
(4) Both the master and slave devices contain a serial shift register, and the master initiates a data transfer by writing a byte to its SPI serial register. The register transmits the byte to the slave device via the MOSI signal line, and the slave returns the contents of its shift register to the master via the MISO signal line, effectively exchanging the contents of the two shift registers.
(5) Write and read operations of the slave device are synchronized, making SPI a highly efficient protocol.
(6) If only a write operation is performed, the master can ignore the received byte; conversely, if the master wants to read a byte from the slave device, it must send an empty byte to trigger the slave’s transmission.
16. IIC Interface
(1) The IIC bus is a high-performance multi-master bus with bus arbitration and synchronization functions for high and low-speed devices.
(2) The IIC bus requires two lines: Serial Data Line (SDA) and Serial Clock Line (SCL).
(3) Each device on the bus has a unique address for identification, and each device can act as either a transmitter or receiver (depending on the device’s function).
(4) There are four operating modes for the IIC bus: master transmit, master receive, slave transmit, and slave receive.
(5) There are three types of signals during the data transfer process of IIC:
A. Start signal: SDA transitions from high to low while SCL is low.
B. Stop signal: SDA transitions from low to high while SCL is low.
C. Acknowledge signal: The receiver sends a specific low level to the transmitter after receiving 8 bits of data during the ninth pulse.
(6) The master device sends a start signal and immediately sends a slave address to notify the slave device with which it will communicate. One byte of address includes 7 bits of address information and 1 bit of transmission direction indicator; if the 7th bit is 0, it indicates a write operation; if it is 1, it indicates a read operation.
(7) Each byte transmitted on the SDA line is 8 bits long, and there is no limit on the number of bytes transmitted in each transmission. The first byte after the start signal is the address field, and each transmitted byte is followed by an acknowledgment bit (ACK); the most significant bit (MSB) of the serial data is sent first.
(8) If the data receiver cannot accept any more data, it can interrupt the transmission by keeping SCL low, forcing the data sender to wait until SCL is released again. This allows for synchronization between high and low-speed devices.
(9) The working process of the IIC bus: SDA and SCL are both bidirectional. When idle, both SDA and SCL are high; only when SDA goes low and then SCL goes low does the data transfer on the IIC bus begin. Each bit transmitted on the SDA line is sampled on the rising edge of SCL, and that bit must remain valid until SCL goes low again, after which the next bit is transmitted before SCL goes high again, indicating the end of data transmission.
17. Ethernet Interface
(1) The most commonly used Ethernet protocol is the IEEE802.3 standard.
(2) Transmission encoding: Manchester encoding and differential Manchester encoding.
A. Manchester encoding: Each bit has a level transition in the middle, with a transition from high to low representing “0” and from low to high representing “1”.
B. Differential Manchester encoding: Each bit has a level transition in the middle, using the presence or absence of a transition at the start of each code element to represent “0” or “1”; a transition indicates “0” and no transition indicates “1”.
(3) Compared to Manchester encoding, differential Manchester encoding is simple, while it offers better noise suppression performance.
(4) Characteristics of Ethernet data transmission:
A. All data bits are transmitted starting from the low bit, and the bit stream is transmitted using Manchester encoding.
B. Ethernet is based on a collision detection bus multiplexing method, executed automatically by hardware.
C. The length of the transmitted data includes the destination address (DA) + source address (SA) + type field (TYPE) + data segment (DATA) + padding bits, with a minimum length of 60B and a maximum length of 1514B.
D. Typically, Ethernet cards can receive data addressed to three types of addresses: broadcast address, multicast address, and its own address.
E. The physical addresses of any two network cards are different and unique in the world, assigned by a specialized organization.
(5) There are two methods to implement embedded Ethernet interfaces:
A. Embedded processor + network card chip (e.g., RTL8019AS, CS8900, etc.)
B. Processors with Ethernet interfaces.
(6) TCP/IP is a layered protocol, divided into: physical layer, data link layer, network layer, transport layer, and application layer. Each layer implements a specific function, corresponding to one or several transmission protocols, and each layer operates as an independent data packet relative to its lower layer. The protocols at each layer are as follows:
A. Application layer: BSD sockets.
B. Transport layer: TCP, UDP.
C. Network layer: IP, ARP, ICMP, IGMP
D. Data link layer: IEEE802.3 Ethernet MAC
E. Physical layer: Binary bit stream.
(7) ARP (Address Resolution Protocol)
A. The network layer uses 32-bit addresses to identify different hosts (i.e., IP addresses), while the link layer uses 48-bit physical addresses (MAC) to identify different Ethernet or token ring interfaces.
B. The function of ARP: to convert from IP address to corresponding physical address.
(8) ICMP (Internet Control Message Protocol)
A. It is used by the IP layer to exchange error messages and other important control information with other hosts or routers.
B. ICMP messages are transmitted within IP packets.
C. Network diagnostic tools ping and traceroute are actually ICMP protocols.
(9) IP (Internet Protocol)
A. IP operates at the network layer and is the core protocol of the TCP/IP protocol family.
B. All TCP, UDP, ICMP, and IGMP data are transmitted in IP packet format.
C. TTL (Time To Live): Specifies the lifetime of IP packets (the number of routers the packet can pass through).
D. IP provides an unreliable, connectionless service for data packet delivery, which is efficient and flexible.
a. Unreliable: It cannot guarantee that packets will successfully reach their destination; any required reliability must be provided by the upper layer (such as TCP). If an error occurs, IP has a simple error handling algorithm—discard the packet and send an ICMP message to the source.
b. Connectionless: IP does not maintain any state information about subsequent packets. Each packet is processed independently. IP packets can be received out of order.
(10) TCP (Transmission Control Protocol)
TCP is a reliable, connection-oriented transport layer protocol that provides high reliability end-to-end data communication between two hosts.
(11) UDP (User Datagram Protocol)
UDP is a connectionless, unreliable transport layer protocol that does not guarantee that packets will reach their destination; reliability is provided by the application layer. UDP has low overhead and is more suitable for use in low-end embedded fields compared to TCP.
(12) Ports: TCP and UDP use 16-bit port numbers to identify upper-layer users, i.e., application layer protocols. For example, the TCP port number for FTP service is 21, for Telnet service is 23, and for TFTP service is 69.
18. CAN Bus Interface
(1) CAN (Control Area Network) bus is a multi-master serial communication bus, one of the most widely used field buses internationally, initially used for electronic control networks in automotive environments. In a single network formed by a CAN bus, ideally, any number of nodes can be connected, although in practice, the number of nodes is limited by the electrical characteristics of the network hardware.
(2) Bus signals are transmitted using differential voltage. Two signal lines are called CAN_H and CAN_L, with a static value of around 2.5V, indicating logic 1, also called