Siemens SMART200 PLC High-Speed Counter Operating Modes

1. Overview of High-Speed Counters

The S7-200 SMART PLC integrates hardware high-speed counters that operate independently of the CPU scan cycle. The standard CPU (firmware version V2.3+) supports 6 channels of high-speed counters, while the compact CPU supports 4 channels. The C-type CPU has a maximum counting frequency of 100kHz, and the S-type CPU reaches 200kHz, depending on the model and firmware version.

2. Classification of Operating Modes (8 Types)

Based on the type of input signal and control method, the modes are divided into four main categories:

Mode Group	Mode Number	Description	Key Features
Single-phase Internal Direction	0	No external reset	Direction controlled by SMB37.3, 1=increment, 0=decrement
1	With external reset	Supports external reset signal (I0.4 high/low level effective)
Single-phase External Direction	3	No external reset	Direction controlled by external input (e.g., I0.1) level
4	With external reset	External direction + reset function
Dual-phase Increment/Decrement Counting	6	No external reset	Increment/decrement counting pulses controlled by two inputs
7	With external reset	Dual-phase input + external reset
A/B Quadrature Counting	9	No external reset	A/B phase quadrature input, supports 1X/4X frequency multiplication
10	With external reset	Quadrature input + external reset (Z phase)

3. Key Technical Parameters

Input Filter Time

Must be set in the system block, default 6.4ms supports only 78Hz, high-speed applications should be changed to 0.2~3.2μs (corresponding to 200kHz).
Interrupt Events

Current value = preset value (events 12-16)
Direction change (events 27-28)
External reset (event 28)

Address Allocation

Control byte: SMB37 (HSC0), SMB47 (HSC1), etc.
Current value: SMD38 (HSC0), HC0 (read-only)
Preset value: SMD42 (HSC0)

4. Typical Application Wiring

Taking the A/B quadrature encoder (mode 10) as an example:

A phase → I0.0 (Clock A)
B phase → I0.1 (Clock B)
Z phase → I0.4 (Reset)
Encoder power supply: 24V DC

5. Programming Key Points

Initialization Steps

plaintext

// HSC0 mode 10 initialization example

SMB37 = 16#FC; // Enable counting, update current value/preset valueSMD38 = 0; // Clear current valueSMD42 = 1000; // Preset value 1000HDEF 0, 10; // Define HSC0 as mode 10ATCH INT_0, 12; // Bind CV=PV interruptENI; // Enable global interruptsHSC 0; // Start counter

Interrupt Handling

Update preset value or perform reset operation in the interrupt program.

6. Firmware Version Differences

V2.3+: Standard CPU supports 6 channels of HSC, new frequency measurement mode added
V2.8+: Supports 16 channels of PID, ST60 pulse axis expanded to 4 channels

Note: HSC1/HSC3 only support mode 0, input points cannot be shared with other high-speed functions.

1. Hardware Wiring Diagram

Figure 1: Wiring diagram for HSC0 mode 10 (A/B quadrature with reset), I0.0 connected to A phase, I0.1 connected to B phase, I0.4 connected to reset signal

2. Operating Mode Timing Diagram

Figure 2: Timing waveform of single-phase counter with internal direction control (mode 0/1), showing counting direction switch and interrupt trigger points

Figure 3: 4X frequency working principle of A/B phase quadrature counting (mode 9/10), A/B phase pulse phase difference of 90° for direction determination

3. Programming Example Screenshots

Figure 4: Step interface for configuring HSC0 using STEP 7-Micro/WIN SMART wizard, including mode selection and parameter settings

Figure 5: Example of HSC initialization subroutine, including control byte settings, interrupt binding, and counter start command

8. Mode Selection Decision Tree

mermaid

graph TD A[Select Counter Type]-->|Single-phase Input| B(Internal Direction Control) A -->|Single-phase Input| C(External Direction Control) A -->|Dual-phase Input| D(Increment/Decrement Counting) A -->|Quadrature Encoding| E(A/B Phase Counting) B --> F[Mode 0: No Reset] B --> G[Mode 1: With Reset] C --> H[Mode 3: No Reset] C --> I[Mode 4: With Reset] D --> J[Mode 6: No Reset] D --> K[Mode 7: With Reset] E --> L[Mode 9: No Reset] E --> M[Mode 10: With Reset]

High-Speed Counter Mode Selection Decision Process

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