RV April Technical Progress

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RV April Progress Report

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The sPMP community has engaged in intense discussions regarding the new Spec (v0.9.7)

Main updates in the Spec:

• Refinement of indirect CSR access methods: The specification has further optimized the access methods for indirect CSRs (Control and Status Registers). This improvement is based on community feedback, particularly adjustments to the details of related operations.

• New software guidelines chapter: A new software development guide has been added to help developers better understand and implement SPMP. This chapter was co-authored by several contributors, including Thomas, José, and Sandro.

• Other minor modifications and improvements: In addition to the significant updates mentioned above, other details in the specification have also been adjusted slightly to enhance the clarity and standardization of the document.

Summary of key issues:

• Indirect register access: Although there has been discussion about packing and unpacking register fields, members generally agree that direct access methods are more efficient for hardware. The use of indirect registers increases software complexity and may lead to performance bottlenecks, especially during context switching.

• Dynamic changes to SPMP rules: Regarding the necessity of dynamically updating SPMP rules, while some members believe that the cost of updating configuration registers is high, it is essential to maintain the consistency of SPMP rules for security reasons, ensuring the isolation of each process.

• ARC review and specification stabilization: The final stabilization of the SPMP specification and the ARC review are the next important steps aimed at ensuring the implementability and broad acceptance of the specification.

Author: Huang Zhibai

[Proposal] Allow writing arbitrary values to mask/tail agnostic elements

The ratified RVV 1.0 requirement states that during mask/tail agnostic operations, the masked and tail elements should not be written as all 0xff values. There has been a proposal to relax this requirement. Discussions have focused on whether such a modification would break existing code and whether there are security risks.

Link:

https://lists.riscv.org/g/sig-vector/topic/112309019

Author: Xu Kailiang

Follow-up on RISC-V architecture support

RISC-V With Linux 6.15 Adds Support For BFloat16 “BF16” Instructions

Link:

https://www.phoronix.com/news/Linux-6.15-RISC-V

GCC Compiler Adds Targeting Support For XuanTie RISC-V CPUs

Link:

https://www.phoronix.com/news/GCC-XuanTie-RISC-V-CPUs

Ubuntu Adds Support For A New Low-Cost RISC-V Board: The OrangePi RV2 8GB For ~$64

Link:

https://www.phoronix.com/news/Ubuntu-Linux-On-OrangePi-RV2

Orange Pi RV2 Benchmarks: The Most Performant RISC-V Board For Less Than $100 With 8 Cores + 8GB RAM

Link:

https://www.phoronix.com/review/orange-pi-rv2-benchmarks

Authors: Xu Kailiang, Xue Songtao

New version of CPUBench officially released, fully supports RISC-V instruction architecture, completing the last piece of the “puzzle” for fully compatible benchmark instruction sets

The China Electronics Standardization Institute has officially released the latest version of CPUBench v1.3.1.

CPUBench is the first domestically developed general-purpose CPU performance evaluation benchmark tool led by the China Electronics Standardization Institute, jointly developed with industry chip manufacturers, system manufacturers, and industry users such as Haiguang, Huawei, Loongson, Feiteng, Zhaoxin, and Shenwei. It can accurately measure the computational performance of CPU products in typical application scenarios across various business fields and can be used to guide the design optimization, specification selection, and market procurement of computing products (CPU, computer systems, etc.), playing an important role in the development of the computing industry.

The new version of CPUBench has made significant breakthroughs in instruction set architecture support, being the first to achieve support for the RISC-V instruction set architecture. Compatibility verification has been completed for RISC-V processor products from companies such as Supermicro Technology and Sanneng Technology, and verification has been completed on China Telecom’s “Beihai” RISC-V cloud computing experimental platform, completing the last piece of the fully compatible landscape for mainstream instruction architectures, allowing RISC-V architecture processors to be compared with other instruction set architectures based on “the same standard, the same tool” for performance analysis.

Link:

https://mp.weixin.qq.com/s/RKsl_aPbBDT_m5w-TK9Wqg

Author: Wei Zhixiang

Discussion on the classification and standardization of software prefetching events in RISC-V PMU

Content overview:

In the design of the RISC-V Performance Monitoring Unit (PMU), how to treat software prefetching events has sparked technical discussions. The key question is: should software prefetching be classified similarly to demand loads, hardware prefetching, or treated as an independent event?

Discussion points:

Background and issues: Beeman Strong (Rivos Inc.) proposed that the behavior definition of software prefetching in the PMU needs to be clarified, such as whether it should be counted in cache access, prefetch validity, and other metrics to evaluate the effectiveness of software optimization.

Core viewpoints:

• Greg Favor emphasized that software prefetching should be distinguished from hardware prefetching and demand loads for reasons including controllability: software prefetching is directly controlled by developers, while hardware prefetching is determined by microarchitecture implementation. Optimization goals: the core of performance events is to provide feedback to software to help optimize code logic. Mixing statistics may confuse the impact of different prefetch mechanisms.

• It is suggested to define independent events for software prefetching (such as SW_PREFETCH_ACCESS and SW_PREFETCH_MISS) to monitor its behavior and efficiency separately.

Future directions:

• Further discussion is needed on specific event definitions (such as whether to distinguish prefetch types, cache levels) and to coordinate performance sampling (Performance Event Sampling TG) with PMU standardization work.

• The design of independent events may become a key extension of the RISC-V performance analysis toolchain, assisting developers in fine-tuning data prefetch strategies.

Summary:

The current consensus leans towards viewing software prefetching as an independent category to provide clearer performance insights and enhance RISC-V’s optimization capabilities in high-performance computing scenarios.

Link:

https://lists.riscv.org/g/sig-perf-analysis/

topic/software_prefetching/112217633

Author: Wei Zhixiang

Android 15 successfully runs on high-performance RISC-V platforms

Main updates in the Spec:

• Andes + Imagination demonstrated a complete Android 15 stack smoothly on the Voyager development board (quad-core AX45MP 2.2 GHz, 512-bit vector unit NX27V, BXT-32-1024 GPU) on 2025-04-29; achieving native Launcher, Play Services, and 3D game operation for the first time on a RISC-V platform.

• Using the Linux 6.15-rc mainline kernel, enabling RISC-V Vector (V) and BF16 extensions; graphics layer supports Vulkan 1.3 / OpenCL 3.0, dual 4K @ 60 Hz output, with a measured Geekbench 6 Multi score of approximately 1350 (close to Cortex-A55).

• The platform complies with the RVA23 hardware and software specifications; all patches have been submitted to AOSP/LKML, expected to merge in 6.16; officially regarded as a milestone for RISC-V’s entry into the mobile terminal and high-end embedded market.

Discussion and feedback:

• The community generally believes that this move significantly enhances the feasibility of RISC-V in smart devices, proving that the open-source ISA can support complex GUI and multimedia workloads.

• Some developers pointed out that the AX45MP is a mid-range performance core, looking forward to the upcoming tape-out of out-of-order 3 GHz RISC-V CPUs and open-source GPU drivers to further consolidate ecosystem openness.

• The success of the demonstration is attributed to ISA standardization (RVA23 / vector extension) and industry collaboration; Imagination stated that a complete GPU SDK for RISC-V will be released by the end of the year to lower the porting threshold.

• Several ODM and SoC manufacturers (Allwinner, Longsys, StarFive) have announced follow-ups, planning to launch the first batch of RISC-V mobile phones and box reference designs in 2026.

Link:

https://www.andestech.com/en/news/2025-04-29-riscv-android15-demo

Author: James

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