(Source: Aijiwe) 
The global shipment of RISC-V chips has surpassed 10 billion. Its open-source and free characteristics, along with a “Lego-style” modular design, provide developers with unprecedented freedom to flexibly combine instruction sets and create all-scenario chips ranging from IoT to AI accelerators. This has attracted participation from numerous global enterprises, research institutions, and developers, with China boasting the largest application market and the most active developer community, driving the strong rise of this architecture.However, a key bottleneck in the domestic development of RISC-V has already emerged—the lack of Electronic Design Automation (EDA) tools. As the Technical Director of Chipone Technology stated: “RISC-V has opened the era of customized chip design, but our EDA tools are still stuck in the assembly line stage.”This significant gap between tool capabilities and architectural potential reveals the core of the problem. It requires a shift from a closed, unidirectional process to an open, collaborative ecosystem, from passive adaptation to standard processes to proactive optimization for customized scenarios, and from fragmented breakthroughs in single-point technologies to deep innovation at the system level.Breaking the deadlock requires enhancing four core capabilities.The modular characteristics of the RISC-V architecture, which combine the basic instruction set with extended instructions, impose multidimensional technical requirements on EDA tools.Firstly, tools must efficiently support the development of user-defined instructions (Custom Instructions) and enable rapid verification and implementation of microarchitecture optimizations. Secondly, in the face of verification space explosion caused by fragmented configurations, the toolchain must be capable of handling massive combinations of scenarios, covering complex scenarios such as verification of different extended instruction set combinations and multi-core consistency verification. Thirdly, deep collaborative optimization among compilers, operating systems, and hardware relies on EDA tools to provide efficient virtual prototypes and early performance analysis capabilities to support design iterations at the system level. Fourthly, the demand for built-in security mechanisms in chips (such as memory encryption, root of trust, etc.) is increasingly prominent across all application scenarios from IoT to data centers, requiring EDA tools to support automated design and verification processes for secure architectures.Based on the above requirements, domestic EDA vendors need to focus on enhancing four core capabilities.From an industrial value perspective, a fully autonomous toolchain is the core pillar for breaking free from external dependencies and ensuring the autonomous and controllable nature of the RISC-V ecosystem. Only by achieving full-process autonomy from RTL design, functional verification, physical implementation to sign-off can we avoid being constrained by external tool barriers in critical stages of RISC-V chip design, ensuring the freedom and security of customized innovation.
In enhancing RISC-V specific enhancement capabilities, domestic EDA tools must emphasize specificity. They should automatically complete the recognition of custom instructions, RTL generation, and compiler integration to accelerate the conversion from algorithms to hardware; they should have a domestic configurable processor generation platform similar to Codasip Studio, enabling “checkbox” generation of RISC-V SoCs to lower design thresholds; and they should build heterogeneous computing verification platforms to address co-simulation and cross-domain communication issues between RISC-V cores and GPUs or AI accelerators.Strengthening system-level design capabilities requires building two core technical supports: on one hand, a virtual prototype development environment based on QEMU/SystemC must be created to achieve early modeling and pre-positioning of software debugging processes. For example, by referencing the virtualization experience of Loongson’s LoongArch architecture, it should support completing over 80% of software debugging work before the Linux system starts, significantly shortening the soft-hard collaborative development cycle; on the other hand, the ability to predict power consumption and performance at the RTL stage must be established, referencing the technical paths of tools like Ansys PowerArtist to achieve accurate forecasting of chip PPA (Performance, Power, Area) metrics, thereby reducing the number of iterations in the backend design phase and improving overall design efficiency.Enhancing ecological collaboration capabilities hinges on building open interface standards. An open API with domestic autonomous characteristics (such as Python/TCL interfaces) must be developed to achieve compatibility and interoperability with mainstream ecosystems through standardized interface design, enabling seamless integration with open-source EDA tools like KLayout and OpenROAD, while also providing a flexible foundation for secondary development for third-party developers, thereby breaking down barriers between tools and forming a collaborative and efficient ecological system.In fact, domestic EDA vendors have made significant progress in the RISC-V field. Hejian Technology’s verification system supports the efficient verification of RISC-V processors such as “Xiangshan,” enabling rapid debugging of multi-core systems, and has launched a new generation of tools to enhance early design efficiency; Tanggu Intelligent has developed AI-driven front-end design verification tools, constructing a full-process toolchain covering RTL to layout, with its prototype verification products supporting large-scale designs and participating in the construction of an open-source chip service platform; Chipone’s verification platform has improved debugging capabilities and efficiency in RISC-V processor verification; and Sierxin has contributed to the construction of the RISC-V ecosystem through IP evaluation.These achievements provide practical tool support for domestic RISC-V chip design.Mergers and acquisitions break the “small and scattered” pattern.Recently, Synopsys completed the acquisition of simulation EDA company Ansys for $35 billion, which is of great significance for the development of RISC-V.Before the acquisition, Synopsys had already laid out in the RISC-V field, while Ansys had significant advantages in its simulation and analysis product portfolio. After the acquisition, the advantages of both parties will be integrated to accelerate the completion of the full-process toolchain for RISC-V design. For example, in the architecture simulation phase, utilizing Ansys’s multi-physics simulation technology will allow developers to more accurately simulate the performance of RISC-V architecture under different scenarios and optimize designs in advance; in the hardware verification phase, combining Synopsys’s existing verification tools with Ansys’s analytical capabilities can efficiently detect potential issues in hardware designs, significantly improving the efficiency from architecture simulation to hardware verification.At the same time, Synopsys is actively integrating the acquired technology with its ecosystem and open-source community. Synopsys has a large customer base and a complete ecosystem, and by integrating Ansys technology, it can provide RISC-V developers with a more comprehensive and convenient development environment, lowering the usage threshold. In the open-source community, Synopsys will develop tool plugins or modules compatible with the RISC-V open-source community based on the acquired technology, promoting communication and collaboration among developers within the community, accelerating the landing of RISC-V chips in embedded and high-performance computing scenarios, and pushing the global RISC-V ecosystem from technological exploration to a new stage of industrial application.In the first half of 2025, the domestic EDA industry will continue the integration trend of recent years, accelerating the strategic direction of technology integration, expanding product lines, and enhancing comprehensive competitiveness to safeguard the large-scale application of RISC-V.
In the RISC-V field, the verification phase, especially hardware acceleration verification, is a key area that domestic full-process EDA vendors urgently need to tackle. Sierxin has a strong technical foundation in this area, and its products can significantly enhance the efficiency and accuracy of chip verification, meeting the stringent requirements of complex chip designs.In 2025, Gaon Electronics completed the 100% acquisition of Sierxin (S2C) through cash and equity. Previously, Gaon Electronics had strong capabilities in point tools such as SPICE simulators (NanoSpice), yield analysis (Yield Explorer), and modeling and testing (BSIMProPlus), but was somewhat weak in the verification phase. Sierxin, on the other hand, is globally leading in FPGA prototype verification and hardware acceleration simulation, with a significant market share in China. This acquisition greatly enhances Gaon Electronics’ capabilities in digital circuit design and verification backend, filling product line gaps, and in RISC-V processor design, Sierxin’s technology can accelerate the verification process, quickly identify design flaws, and ensure the correctness of key designs such as instruction set extensions and multi-core architecture collaboration, facilitating efficient iteration of RISC-V chips.Domestic vendors are also looking overseas for quality asset acquisitions to enhance their technical strength. In March 2025, Chip Vision, focused on chip analysis (reverse engineering/IP analysis) and design services, acquired a specific point tool asset portfolio from an overseas EDA company. Chip Vision aims to supplement the core EDA technology stack required for chip analysis services, enhancing technical barriers and automation capabilities. The rapid development of the RISC-V ecosystem has raised the requirements for chip analysis technology, and with the acquisition of these specific point tool technologies, Chip Vision is expected to extend its service capabilities to support positive design for RISC-V chips or expand into more specialized analysis fields, such as accurately analyzing the operational logic of RISC-V custom instruction sets in chips, providing key technical support for optimizing RISC-V chip designs and improving performance reliability.The highly anticipated acquisition of a controlling stake in Chip and Semiconductor Technology (Shanghai) Co., Ltd. by Huada Jiutian was announced to be terminated on July 9, but Huada Jiutian’s layout in mergers and acquisitions and industrial investment continues to advance. Since its listing, the company has acquired Chipda Chip Technology Co., Ltd. and invested in several companies, including Shanghai Akas Electronic Technology Co., Ltd., and has jointly established two industrial funds with professional investment institutions.Chip and Semiconductor is also an excellent high-tech enterprise focused on the development of EDA software tools, with significant technological advantages in RF, high-speed, and multi-physics simulation. Its developed multi-physics engine technology can provide a full-stack integrated system EDA solution from chips to complete systems, supporting advanced packaging of Chiplets.From the merger and acquisition dynamics of domestic EDA companies in the first half of the year, we can clearly observe the deep trends and core demands of industry development: the urgency for EDA companies to improve their business layout. Currently, although there are many companies in the domestic EDA industry, there are few main bodies with revenues exceeding 100 million yuan, presenting an overall “small and scattered” pattern. Through mergers and acquisitions, companies can achieve efficient collaboration of technology, talent, and market resources, breaking the bottleneck of decentralized development; more importantly, this integration promotes the accelerated construction of a self-controllable tool ecosystem alliance in the industrial chain, reducing dependence on single external tools, and laying a solid foundation for the RISC-V chips in China to move from architectural innovation to large-scale landing, helping to form a self-controllable technical closed loop in key areas such as customized instruction development and multi-core verification.