Looking at job postings on recruitment websites and the trends in the chip industry, there are increasing job opportunities related to low-power design, but in reality, there is a shortage of talent with relevant skills, and salaries for these positions have risen significantly in recent years. In summary, learning low-power design is of utmost importance for IC engineers, helping them find their footing in the ever-evolving chip industry!
This time, E Course Network is launching a brand new practical training course“Practice of Low-Power Design for Digital IC Front-End Based on UPF” which includes front-end and verification. The course adopts a teaching method that combines theory with practical engineering,allowing everyone to understand and master UPF design, low-power verification, and finally complete the entire front-end low-power design process combined with a virtual mining machine project.
Course Highlights
1. In-Depth Analysis: Scientifically equipped teaching content, efficient combination of theory and practice.
2. Renowned Instructors: Industry experts personally guide project work, creating a highly engaging atmosphere.
3. Teaching Assistants: Small class teaching model, teaching assistants provide attentive support throughout.
4. Live Q&A: One-on-one real-time interaction to address specific questions.
5. Periodic Testing: Consolidate early learning outcomes and timely help identify gaps.
6. Project Practice: New mining machine project and usage of mainstream EDA tools like VCS NLP and VCLP, remote server experiments, with server usage extended to two months as a bonus.
7. Dual Certification: Unified assessment upon completion, passing the assessment grants a “Moore Elite E Course Network IC Competency Training Certificate”. Outstanding students may also receive a certification from the Shanghai Semiconductor Industry Association.
8. Discounted Price: Limited-time coupons available, with group registration offering greater discounts.
Target Audience
Future engineers entering digital IC front-end design
Individuals wishing to systematically learn UPF and low power
Digital front-end engineers looking to improve their low efficiency and eager for change
Digital front-end engineers needing to drive projects through learning
……
Lead Instructor
Gold Medal Instructor of E Course Network: Simba Chen
Simba Chen has over 10 years of experience in digital IC front-end design, specializing in low-power design technology, and has participated in low-power process design for large-scale mobile chips and automotive edge AI chips, successfully tape out multiple chips, with rich IC project development experience.
Class Schedule
Course starts on July 30, lasting four weeks; four class hours each Sunday
Specific schedule: Morning10:00~12:00
Afternoon 13:30~15:30
Course Outline
|
Serial Number |
Course Content |
Class Hours |
|
1. Power Probability |
Composition of power consumption Using PTPX for power consumption reporting methods Overview of common power optimization strategies, such as clock gating |
1 |
|
2. Power Optimization Strategies |
Power gating Multi-voltage power supply strategy Specific implementation of DVFS, AVS implementationSelection of multi-threshold cell library Low voltage standby Clock tree power optimization strategies |
1 |
|
3. Introduction and Check of UPF |
Low power cell process library Introduction to low power special cells, such as isolation, retention, enable level shifter, AON buffer, power switch Power supply and power supply set Isolation strategy, level shifter strategy, enable level shifter strategy Power mode table Hierarchy UPF flow Retention register Voltage domain and power domain |
4 |
|
4. Introduction and Use of Low-Power Design EDA Tools |
Introduction to VCLP EDA tool Building VCLP UPF check flow |
1 |
|
Introduction to VCS-NLP EDA tool, introduction to Verdi PPA Using VCS-NLP for UPF simulation |
1 |
|
|
5. LAB |
1. Use VCLP and VCS-NLP to improve UPF in CASE1 and CASE2, and complete the correct waveform placement 2. Design of power sequence control process |
1 |
|
6. Memory Low Power |
1. Single rail and dual rail 2. Memory light sleep, deep sleep, and shutdown 3. Memory DVFS control 4. Memory power breakeven time 5. Memory reconfigure register |
1 |
|
7. MCU Low Power Control |
1. AMBA BUS low power design 2. WFI, WFE 3. CPU SLEEPDEEP mode 4. SOC power modes |
1 |
|
8. Mining Machine Project |
1. Bitcoin project introduction 2. Bitcoin project code design introduction 3. Bitcoin project power domain definition 4. Bitcoin project low power simulation 5. Bitcoin project UPF check 6. Bitcoin project power assessment 7. Bitcoin project CDC check |
5 |
Consultation/Registration
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Course Price
Certificate Sample
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