Low Power Design – Power Switch (2) Adding Switch to the Top Level Block

Classification and application of power switches:

Low Power Design – Power Switch

In a recent project, with tight deadlines, we ran two versions, differing in whether to use UPF. The block is implemented normally, and the switch is added at the top level.

​1. UPF

First, let’s analyze the UPF content related to the power switch:

create_power_domain PD_TOP -supply {primary SS_TOP} -element {u_top}

create_power_domain … …

create_power_domain PD_BT -supply {primary SS_BT} -element {u_top/u_core/u_bt_top}

Here, u_top/u_core/u_bt_top refers to the BT module.

create_power_switch BT_SW -domain PD_BT -input_port {VDDP VDD_TOP} -output_port {VDDC VDD_BT} -control_port {EN */u_bt_powon/O} -on_state {BT_ON VDDP {EN}} -off_state {BT_OFF {!EN}}

add_port_state BT_SW/VDDC -state {on 0.72}

add_port_state BT_SW/VDDC -state {off off}

Here, the -domain uses PD_BT, and the input port/output port/control port correspond to the input/output pins of the switch cell. The add_port_state indicates the power supply voltage state of the block.

At this point, there are two issues:

1) The power domain setting for BT_SW is incorrect because PD_BT only includes one module, so adding a switch to PD_BT is not feasible; it can be changed to PD_TOP.

2) Unlike adding a switch within the core, adding a switch to the block at the top level generally selects the maximum drive, so the type of switch cell changes, and the input port/output port/control port must also change accordingly.

2. Create Power Switch Array

Now, let’s discuss the process of adding the switch cell:

1) First, let PD_BT cover the BT module and reserve an area for the switch cell, adding power rails according to different voltage areas.

2) Then, shrink the voltage area of PD_BT to only cover the BT module, allowing PD_TOP to cover the area where the switch cell is added, using:

create_power_switch_array -boundary

to add the switch cell, using -y_pitch and -x_pitch to control the spacing of the switch cells to 0, ensuring they are adjacent without gaps.

create_power_switch_array -power_switch BT_SW -lib_cell */HEADBUFTIE5 -y_pitch 1 -x_pitch 0.5 -boundary {{xx yy} {xx yy}}

3) Finally, manually pull the power strap for the power switch, connect_pg_net to link the switch’s input, and create_pg_vias to create the power via.

connect_pg_nets VDD_TOP [get_flat_pins -all *BT_SW_snps*/VDDG]

create_pg_vias -nets VDD_TOP -from stripe -to_type pwrswitch -from_layer ME5 -to_layer ME2