a) Small power supplies should prioritize copper pouring on signal layers, followed by connections through traces that meet current-carrying requirements;
Small power supplies (those with relatively low current in PCB design) typically need to consider signal integrity and power distribution issues. During layout, priority should be given to copper pouring on signal layers (usually inner layers) to provide connections for ground planes or power planes, as well as signal transmission paths. This can effectively reduce signal crosstalk and transmission delays, improving signal quality.
However, sometimes copper pouring on signal layers may be affected by space constraints or other design requirements, thus requiring trace connections to meet the distribution needs of small power supplies. In this case, the following points should be noted:
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Trace Planning: Ensure that the power traces have a short path and sufficient width to reduce resistance and voltage drop, and minimize electromagnetic interference. Avoid routing traces across high-speed signal lines or sensitive analog sections to prevent interference with their normal operation.
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Area Design: In the layout, leave appropriate areas to place power distribution network components (e.g., capacitors, inductors, etc.) to ensure power stability and noise suppression.
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Inter-layer Connections: If the signal layer cannot meet the power distribution needs, consider inter-layer connections. This may include connecting to ground planes or power planes on other layers through vias to provide better power distribution.
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Partition Design: Divide power distribution and signal areas into different zones and try to keep them separated in the layout to reduce the possibility of mutual interference. This can better manage signal integrity and power noise.
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Comprehensive Consideration: During the layout design process, it is necessary to comprehensively consider factors such as signal integrity, power distribution, EMI (electromagnetic interference), and weigh and optimize according to specific application requirements.
b) If the 12V and 5V power supplies are the input power for switch-mode power supplies, prioritize handling them on signal layers (surface layer, inner signal layers). If it is necessary to segment on the plane layer, do not use it as a reference plane for important signal lines; this can effectively reduce the impact of such “high” voltages on signals;
If the ripple of the input capacitor for the switch-mode power supply is too large, it can cause some hazards.
The switching ripple on 12V is coupled to the 1.1V plane.
The processor on this board is an X86 processor. The core voltage of the X86 processor is compliant with the VID power supply specification. The VID power supply has a relatively large current, generated from the 12V power supply through DCDC. The switching noise from the MOSFET of this VID power supply affects the input 12V of the front stage. All DCDC inputs are part of this 12V power network, so the large external interference generated by the repeated switching of this switch-mode power supply. The adjacent power plane of 1.1V is 12V, and the interference on 12V is coupled to the 1.1V plane.
c) If the segmented power plane is used as a reference plane for signals, the power plane should prioritize being the signal reference plane for the load module; if there are multiple power supplies, prioritize referencing the lower voltage power supply; for example, if DDR3 uses a 1.5V power supply, the 1.5V power plane can be used as the signal reference plane for the DDR3 module, but do not reference other power supplies; (usually DDR3 data references the ground plane, while address control signals reference its power plane)
d) If the power plane and ground plane are closely adjacent, and if the power plane is adjacent to the signal layer, try to add more GND copper on the signal layer and create GND vias;
In PCB design, having the power plane and ground plane closely adjacent is to provide better power distribution and ground lead. When the power plane is adjacent to the signal layer, the following measures are taken to reduce crosstalk and noise between the power plane and the signal layer:
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Increase Ground Copper: Try to increase ground copper on the signal layer, which can be achieved by laying ground copper on the signal layer. Increasing ground copper helps reduce electromagnetic coupling between the signal layer and the power plane and provides better electromagnetic shielding.
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GND vias: Create GND vias between the signal layer and the power plane. These vias connect the ground lead of the signal layer directly to the ground plane, effectively reducing the resistance of the ground return path, lowering the potential fluctuations of the signal line’s ground, and reducing current loops on the ground return path.
Through these measures, the crosstalk and noise between the signal layer and the power plane can be minimized, improving the quality and stability of the signal. This layout design helps ensure circuit performance and reduce potential interference and issues.
e) The width of the segmentation line should be reasonable; the width of the segmentation line is related to the voltage difference between the two power supplies. Generally recommended: width between analog and digital separation: 25mil; width between digital separations: 15mil, can be smaller in some areas; the width of the segmentation line can also be flexibly adjusted based on the space situation on the board, in principle, the larger, the better;
f) The isolation width for chassis ground segmentation should be at least 2mm, adjusted locally as needed, generally not less than 1mm; other signals should be kept away from chassis ground, including signal lines, vias, copper pouring, etc.;
g) If there is a segmentation of the power/ground plane, ensure that the signal lines on adjacent signal layers do not cross the segmentation and try to avoid having high-speed signals crossing over segmented reference planes.
h) Power vias that are segmented should avoid isolation bands, as isolation bands avoid copper, which can lead to these power vias being unconnected;
i) For the power supply in the analog area, to reduce the influence of the power supply on signals, it is generally not recommended to lay extensive power network copper, usually handled on the signal layer, power copper pouring or traces should meet current-carrying requirements, and in other areas, try to lay more ground copper and create ground vias;
j) High voltage power supplies and low voltage power supplies should be partitioned, the greater the distance, the better; avoid high voltage interfering with low voltage power supplies and signals;
k) Common creepage distance recommendations:
i. When voltage < 24V, surface layer covered with solder mask, distance ≥ 0.13mm; surface layer not covered with solder mask, distance ≥ 0.64mm
ii. When 24V ≤ voltage < 48V, primary side distance ≥ 0.5mm, secondary side distance ≥ 0.2mm;
iii. When 48V ≤ voltage < 100V, distance ≥ 1mm
iv. When 100V ≤ voltage < 200V, distance ≥ 1.5mm
v. When 200V ≤ voltage < 400V, distance ≥ 2.5mm
vi. When 400V ≤ voltage < 600V, distance ≥ 3.2mm
vii. When voltage ≥ 600V, distance ≥ 5mm
l) Confirm that the power and ground can carry sufficient current. Check whether the number of vias meets the carrying requirements
(estimation method: outer layer copper thickness 1oz corresponds to 1A/mm line width, inner layer 0.5A/mm line width)
m) To reduce the edge radiation effect of planes, try to meet the 20H principle between the power layer and ground layer.
(If conditions permit, the more the power layer is recessed, the better).
The “20H principle” means ensuring that the edge of the power plane is recessed at least 20 times the distance between the two planes compared to the edge of the ground plane (0V reference plane), where H refers to the distance between the power plane and ground plane, as shown in the figure below.
Why is the 20H principle necessary?
In high-speed PCBs, the power plane and ground plane typically couple RF energy, leading to edge magnetic flux leakage situations, and RF energy (RF current) radiates along the PCB edges. To reduce this coupling effect, all power plane physical dimensions must be smaller than the nearest ground plane dimensions by a factor of 20H.
n) If ground segmentation exists, check to avoid forming loops in the non-segmented ground?
o) Have the different power planes on adjacent layers avoided overlapping placement?
p) Is the isolation for protective ground, GND greater than 4mm?
q) Is there protective ground laid 10~20mm near the panel with connectors, and are the layers connected using staggered double-row vias?
r) Check the effective width of power traces: Are there any interruptions in the positive and negative copper (BGA, dense vias, and whether there are dense vias in high-speed buses), particularly focusing on 0.8mm BGA.
My understanding of the PCB design enhancement process【1】Interest-driven passion
My understanding of the PCB design enhancement process【2】Should hardware engineers draw PCBs themselves?
My understanding of the PCB design enhancement process【3】How long should PCB traces be?
My understanding of the PCB design enhancement process【4】How wide should PCB traces be?
My understanding of the PCB design enhancement process【5】Inner power layers of PCB
My understanding of the PCB design enhancement process【6】Vias
My understanding of the PCB design enhancement process【7】Can PCBs have sharp angles and right angles?
My understanding of the PCB design enhancement process【8】Should dead copper be retained? (PCB islands)
My understanding of the PCB design enhancement process【9】Can vias be placed on pads?
My understanding of the PCB design enhancement process【10】What materials are PCB materials, what does FR4 refer to?
My understanding of the PCB design enhancement process【11】Solder mask, why is green oil mostly green?
My understanding of the PCB design enhancement process【12】Steel mesh
My understanding of the PCB design enhancement process【13】Pre-layout
My understanding of the PCB design enhancement process【14】Key points of PCB layout and wiring
My understanding of the PCB design enhancement process【15】Cross-segment wiring
My understanding of the PCB design enhancement process【16】Reflection of signals
My understanding of the PCB design enhancement process【17】Dirty signals
My understanding of the PCB design enhancement process【18】Surface treatment processes such as gold plating, immersion gold, and tin spraying
My understanding of the PCB design enhancement process【19】Line spacing
My understanding of the PCB design enhancement process【20】Placement of capacitors
My understanding of PCB design enhancement【21】Crosstalk
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