PCB Design Considerations for RK3588 VDD_LOGIC Power Supply
1. The copper width for VDD_LOGIC must meet the current requirements of the chip. The copper connected to the chip’s power pins should be sufficiently wide, and the path should not be too severely interrupted by vias. It is essential to calculate the effective line width and ensure that the path connected to each power PIN of the CPU is adequate.
2. As shown in Figure 1, the decoupling capacitors near the VDD_LOGIC power pins of the RK3588 in the schematic must be placed on the back of the corresponding power pins. The GND pins of the capacitors should be placed as close to the center GND pin of the chip as possible, as shown in Figure 2. The remaining decoupling capacitors should be placed as close to the RK3588 chip as possible and positioned along the path of the power split source.
3. Each power pin of the RK3588 chip’s VDD_LOGIC requires a corresponding via, and the top layer should follow a “zigzag” pattern for cross connections, as shown in Figure 3. It is recommended to use a line width of 10 mil.
Figure 1: Decoupling Capacitors for VDD_LOGIC Power Pins of RK3588
Figure 2: Placement of Decoupling Capacitors on the Back of VDD_LOGIC
Figure 3: Zigzag Connection for VDD_LOGIC
4. The line width for the VDD_LOGIC power supply in the CPU area must not be less than 120 mil, and the width in the peripheral area should not be less than 200 mil. It is advisable to use copper pour to reduce voltage drop caused by routing (other signal vias should not be placed randomly; they must be placed systematically to free up space for power routing, which also benefits the copper pour for the ground layer), as shown in Figure 4.
5. When changing layers for the VDD_LOGIC power supply in the periphery, it is recommended to use as many power vias as possible (more than 8 vias of 10-20 mil) to reduce voltage drop caused by layer changes; the number of GND vias for the decoupling capacitors should match the number of their power vias, otherwise, it will significantly reduce the effectiveness of the capacitors, as shown in Figure 5.
Figure 4: Copper Pour for VDD_LOGIC Power Layer
Figure 5: Copper Pour for Power Layer Underneath the VDD_LOGIC Chip
6. It is recommended to have at least 11 GND vias within a range of 40 mil (distance from center of via to center of via) for the power vias, as shown in Figure 6.
Figure 6: Placement of GND Vias for LOGIC Power
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