PCB Design Considerations for RK3588 VDD_CPU_LIT Power Supply

PCB Design Considerations for RK3588 VDD_CPU_LIT Power Supply

1. The copper width of VDD_CPU_LIT must meet the current requirements of the chip, and the copper connected to the chip power pin must be wide enough. The path cannot be severely segmented by vias; effective line width must be calculated to ensure that the paths connected to each power PIN of the CPU are sufficient.

2. When changing layers for VDD_CPU_LIT power supply, as many power vias as possible should be added (more than 9 vias of 0.5*0.3mm) to reduce the voltage drop caused by layer changes; the number of GND vias for decoupling capacitors should match the number of power vias; otherwise, the effectiveness of the capacitors will be greatly reduced.

3. As shown in Figure 1, the decoupling capacitors near the VDD_CPU_LIT power pins of RK3588 on the schematic must be placed on the back of the corresponding power pins, and the GND PAD of the capacitors should be placed as close to the center GND pin of the chip as possible, as shown in Figure 2. The remaining decoupling capacitors should be placed as close to the RK3588 chip as possible and need to be positioned along the path of power separation sources.

4. For the power pins of RK3588 chip VDD_CPU_LIT, there should be a corresponding via near each pin, and the top layer should follow a zigzag pattern for cross connections, as shown in Figure 3. It is recommended to use a line width of 10 mil.

Figure 1: Decoupling capacitors for VDD_CPU_LIT power pins

Figure 2: Placement of decoupling capacitors on the back of the power pins

Figure 3: Zigzag chain of VDD_CPU_LIT power pins

5. The line width of the VDD_CPU_LIT power supply in the CPU area must not be less than 120 mil, and the width in the peripheral area must not be less than 300 mil. A dual-layer power copper method should be used to reduce the voltage drop caused by routing (other signal layer change vias should not be placed randomly, they must be placed regularly to free up space for power routing, which also benefits the copper coverage of the ground layer, as shown in Figure 4).

Figure 4: Copper coverage situation of VDD_CPU_LIT power layer

6. The number of GND vias within a 40 mil range (center to center distance of vias) for power vias is recommended to be ≧9, as shown in Figure 5.

Figure 5: Placement diagram of LIT power ground vias