The 100ohm feedback resistor needs to be placed close to the output capacitor. One end of the resistor connects to the DC-DC output capacitor, while the other end connects to the VOUT feedback pin of the PMIC, and simultaneously to the farthest load of the same power network as the RK3588 power pins. The width of the feedback line should be 4mil and must run alongside the power copper to avoid interference; the feedback line should be spaced more than 6mil from other signals. The following diagram shows the routing of the VDD_GPU power copper and feedback line, which should be treated similarly for other power lines.
The width of the power copper must meet the current demand of the chip, and the copper connected to the chip power pins must be sufficiently wide. The path cannot be severely interrupted by vias; effective line width must be calculated to ensure that the paths connected to each power PIN of the CPU are adequate. When switching layers for power, as many power vias as possible should be used to reduce voltage drop caused by layer switching; the number of GND vias for decoupling capacitors should match the number of their power vias, otherwise it will greatly reduce the effectiveness of the capacitors. For RK3588 chip power pins, ensure that there is a corresponding via for each Ball, and the top layer should follow a βδΊβ shape (cross pattern) with a recommended line width of 10mil.
Decoupling capacitors located near the RK3588 power pins must be placed on the back of the corresponding power pins, and the GND pad of the capacitor should be as close as possible to the GND Ball at the center of the chip, while other decoupling capacitors should be placed near the RK3588.
For high current, double-layer copper is required to meet the current-carrying requirements. For example, the VDD_CPU_BIG power in the CPU area should not have a total line width less than 300mil, and the width in the peripheral area should not be less than 600mil. It is advisable to use copper pouring to reduce the voltage drop caused by routing (do not place other signal layer switching vias randomly; they must be placed regularly to free up space for power routing, which is also beneficial for ground layer copper pouring).
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