My Night with SPI: The Logic Analyzer’s Limitations

My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

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My Night with SPI: The Logic Analyzer's Limitations

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My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

About Today’s Post

SPI is a high-speed, full-duplex communication bus.
SPI communication uses 3 buses and a chip select line: SCK, MOSI, MISO, and the chip select line is SS.

My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

No matter how many slave devices there are, they all share these 3 buses; each slave device has its own NSS signal line, which occupies one pin of the master. Thus, the number of slave devices determines the number of chip select signal lines.
SPI communication starts with the NSS line pulled low and ends with the NSS line pulled high.
The basic concept of SPI communication will not be elaborated here; you can look it up online.
The MOSI and MISO data lines transmit one bit of data during each clock cycle of SCK, and data input and output occur simultaneously.
Let’s first look at the communication timing of SPI:

My Night with SPI: The Logic Analyzer's Limitations

1. Start and stop signals of communication:

The NSS signal line transitions from high to low, which is the start signal for SPI communication.

The NSS signal transitions from low to high, which is the stop signal for SPI communication, indicating the end of the communication and cancelling the selection state of the slave.

2. Data Validity

SPI uses the MOSI and MISO signal lines to transmit data and the SCK signal line for data synchronization.
The MOSI and MISO data lines transmit one bit of data during each clock cycle of SCK, and data input and output occur simultaneously. There is no strict requirement on whether the MSB or LSB is sent first, but it must be ensured that both SPI communication devices use the same protocol, which is generally MSB first.
Observe the labeled points 2, 3, 4, and 5 in the diagram; the data on MOSI and MISO changes output during the rising edge of SCK and is sampled during the falling edge of SCK. Thus, at the moment of the falling edge of SCK, the data on MOSI and MISO is valid, with a high level representing data ‘1’ and a low level representing data ‘0’.
At other times, the data is invalid, and MOSI and MISO are prepared for the next data representation.
Each SPI data transmission can be in units of 8 bits or 16 bits, with no limit on the number of units transmitted at once.

My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

My Night with SPI: The Logic Analyzer's Limitations

The main mode send/receive process and event description are as follows:

  1. Control the NSS signal line to generate the start signal (not shown in the diagram);

  2. Write the data to be sent into the “Data Register DR”; this data will be stored in the send buffer;

  3. Communication begins, SCK clock starts running. MOSI sends the data from the send buffer bit by bit; MISO stores the data bit by bit into the receive buffer;

  4. When a frame of data has been sent, the “TXE flag” in the “Status Register SR” is set to 1, indicating that a frame has been transmitted and the send buffer is empty; similarly, when a frame of data has been received, the “RXNE flag” is set to 1, indicating that a frame has been transmitted and the receive buffer is not empty;

  5. Wait for the “TXE flag” to be 1; if more data needs to be sent, write data again to the “Data Register DR”; wait for the “RXNE flag” to be 1; the contents of the receive buffer can be obtained by reading the “Data Register DR”.

If we have enabled the TXE or RXNE interrupt, when TXE or RXNE is set to 1, it will generate an SPI interrupt signal, entering the same interrupt service function. Once in the SPI interrupt service program, you can check the register bits to understand which event occurred and handle them accordingly. DMA can also be used to send and receive data from the “Data Register DR”.

My Night with SPI: The Logic Analyzer's Limitations

The following diagram shows the refresh timing collected using a logic analyzer, but the sampling deviation is too large; it can only give a rough idea and is not recommended as a reference.

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(Disclaimer: This article is compiled to disseminate relevant technical knowledge; some collected materials are copyrighted by their original authors)

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