The motor driver IC transmits a large amount of current while dissipating a significant amount of electrical energy. Typically, energy is dissipated into the copper areas of the printed circuit board (PCB). To ensure sufficient cooling of the PCB, special PCB design techniques are required. This article provides some general recommendations for PCB design of motor driver ICs.

Use Large Copper Areas!

Copper is an excellent conductor of heat. Since the substrate material of the PCB (FR-4 glass epoxy) is a poor conductor, from a thermal management perspective, the more copper area on the PCB, the better the heat conduction.

A 2-ounce (68-micron thick) copper plate conducts heat better than a thinner copper plate. However, thick copper is not only expensive but also difficult to achieve fine geometries. Therefore, a 1-ounce (34-micron thick) copper plate is often used. The outer layers often use 1/2 ounce of copper plating, with a thickness of up to 1 ounce.

In multilayer boards, inner layers often use solid copper plates for better heat dissipation. However, since their plane layers are usually located at the center of the circuit board stack, heat may be trapped inside the circuit board. Therefore, copper areas can be added to the outer layers of the PCB, connected to the inner layers via vias to transfer heat out.

Heat dissipation is also more challenging in double-sided PCBs due to traces and components. Therefore, motor driver ICs should use as much solid copper plate and vias that facilitate heat dissipation as possible. Casting copper on both sides of the outer layers and connecting them using vias can spread heat across different areas separated by traces and components.

Traces Must Be Wide—The Wider, The Better!

Since the current flowing through the motor driver IC can be large (sometimes exceeding 10A), careful consideration should be given to the PCB trace width connected to the chip. The wider the trace, the lower the resistance. The trace width must be adjusted to ensure that the resistance in the trace does not cause excessive energy dissipation leading to increased trace temperature. However, traces that are too thin can easily burn out like a fuse.

Designers typically use the IPC-2221 standard to calculate appropriate trace widths. This specification includes a chart showing the copper cross-sectional area for different current levels and their allowable temperature rise, allowing for conversion of trace width based on the given copper layer thickness. For example, a 1-ounce thick copper layer carrying 10A of current requires a trace width of exactly 7mm to achieve a 10°C temperature rise, while only a 0.3mm width is needed for a 1A current.

According to this method, it seems impossible to run 10A of current through a micro IC pad.

Therefore, it is essential to understand the recommendations for constant width long PCB traces in the IPC-2221 standard. If a trace connects to a larger trace or copper area, using a short segment of PCB trace to carry a larger current has no adverse effects. This is because the resistance of a short and narrow PCB trace is very low, and the heat generated is absorbed into the wider copper area. As shown in Figure 1: even if the heat sink pad in this device is only 0.4mm wide, it can carry up to 3A of continuous current because the trace is widened as much as possible to approach the actual width of the device.

Figure 1: Widening PCB TracesSince the heat generated by narrower traces will conduct to the wider copper areas, the temperature rise of narrow traces can be negligible.Traces embedded in the inner layers of the PCB do not dissipate heat as effectively as outer layer traces, due to the poor thermal conductivity of the insulator. For this reason, the width of inner layer traces should be twice that of outer layer traces.Table 1 provides rough recommendations for trace widths of long traces (greater than 2cm) in motor driver applications.

Table 1: PCB Trace WidthsIf space allows, wider traces or copper pours can minimize temperature rise and reduce voltage drop.Thermal Vias—The More, The Better!Vias are small plated holes typically used to transfer signal traces from one layer to another. As the name suggests, thermal vias transfer heat from one layer to another. Proper use of thermal vias can effectively help PCB heat dissipation, but many practical issues need to be considered in production.Vias have thermal resistance, which means that whenever heat flows through, there will be a certain temperature difference across the vias, measured in degrees Celsius per watt. Therefore, to minimize thermal resistance and improve the heat dissipation efficiency of vias, they should be designed to be larger, and the copper area inside the vias should be as large as possible (see Figure 2).Figure 2: Cross-section of a ViaWhile large vias can be used in open areas of the PCB, they are often placed inside heat sink pads to directly dissipate heat from the IC package. In this case, large vias cannot be used, as oversized plated holes can lead to “solder wicking,” where the solder used to connect the IC to the PCB flows down into the vias, causing poor solder joints.There are several ways to reduce “solder wicking.” One method is to use very small vias to minimize the solder that can flow into the hole. However, the smaller the via, the higher the thermal resistance, so to achieve the same heat dissipation performance, more small vias would be needed.Another technique is to “cover” the vias on the back of the PCB. This requires removing the opening of the solder mask layer on the back panel, allowing the solder mask material to cover the vias. The solder mask layer will cover small vias, preventing solder from wicking into the PCB.However, this brings another issue: flux residue. If the solder mask layer covers the vias, flux can remain inside the vias. Some flux formulations are corrosive, and if not removed for a long time, they can affect the reliability of the chip. Fortunately, most modern no-clean flux processes are non-corrosive and do not cause problems.It should be noted that thermal vias themselves do not have cooling functions; they must be directly connected to copper areas (see Figure 3). Figure 3: Thermal ViasIt is recommended that PCB designers collaborate with SMT process engineers from PCB assembly factories to determine the optimal via sizes and constructions, especially when the vias are located within heat sink pads.Soldering Heat Sink PadsIn TSSOP and QFN packages, large heat sink pads are soldered to the bottom of the chip. These pads are directly connected to the back of the die for heat dissipation. The pads must be soldered well to the PCB to dissipate power.The IC datasheet may not specify the solder paste opening for the pads. Typically, SMT process engineers have their own set of rules about how much solder to place and what shape to use for the via templates.If the opening is the same size as the pad, more solder will be required. When the solder melts, its tension can cause the device surface to bulge. Additionally, it can cause solder voids (cavities or gaps inside the solder). Solder voids occur when volatile substances in the flux evaporate or boil during the solder reflow process, leading to solder separation at the joint.To solve these issues, for pads larger than approximately 2mm², solder paste is usually deposited in several smaller square or circular areas (see Figure 4). Distributing solder across multiple smaller areas can help the volatile substances in the flux to evaporate more easily, preventing solder separation.Figure 4: QFN Solder ToolAgain, PCB designers are advised to collaborate with SMT process engineers to determine the correct solder mask opening for heat sink pads. Online papers can also be referenced.Component PlacementThe component placement guidelines for motor driver ICs are similar to those for other power ICs. Bypass capacitors should be placed as close as possible to the device power pins, and large capacitors should be placed nearby. Many motor driver ICs will use bootstrap capacitors or charge pump capacitors, which should also be placed near the IC.Refer to the component placement example in Figure 5. Figure 5 shows the dual-layer PCB layout of the MP6600 stepper motor driver. Most signal traces are directly laid out on the top layer. Power traces route from the large capacitor to the bypass, using multiple vias on the bottom layer to change layers.Figure 5: MP6600 Component PlacementIn the following text, we will explore detailed packaging methods and PCB layouts for motor driver ICs.In the previous text, some general recommendations for PCB design using motor driver ICs were provided, requiring careful layout of the PCB to achieve proper performance. In the following text, specific PCB layout suggestions will be provided for typical packages of motor drivers.

Lead Package Layout

Standard lead packages (such as SOIC and SOT-23 packages) are commonly used in low-power motor drivers (Figure 6).

Figure 6: SOT 23 and SOIC PackagesTo fully enhance the power dissipation capability of lead packages, MPS adopts a “flip chip lead frame” structure (Figure 7). Without using bonding wires, the chip is bonded to the metal leads using copper bumps and solder, allowing heat to be conducted from the chip to the PCB through the leads.Figure 7: Flip Chip Lead FrameBy connecting larger copper areas to leads carrying larger currents, thermal performance can be optimized. In motor driver ICs, the power, ground, and output pins are typically connected to copper areas.Figure 8: Flip Chip SOIC PCB LayoutFigure 8 shows a typical PCB layout for a “flip chip lead frame” SOIC package. Pin 2 is the device power pin. Note that the copper area is located near the top-layer device, and several thermal vias connect that area to the copper layer on the back of the PCB. Pin 4 is the ground pin and is connected to the surface ground copper area. Pin 3 (device output) is also routed to a larger copper area.

QFN and TSSOP Packages

The TSSOP package is rectangular and uses two rows of pins. The TSSOP package for motor driver ICs typically has a large exposed pad on the bottom for dissipating heat from the device (Figure 9).

Figure 9: TSSOP PackageThe QFN package is a leadless package with a pad around the outer edge of the device and a larger pad in the center of the device’s bottom for absorbing heat (Figure 10).Figure 10: QFN PackageTo dissipate heat from these packages, the exposed pads must be well soldered. The exposed pads are typically at ground potential, allowing them to connect to the PCB ground layer. In the example of the TSSOP package in Figure 11, an array of 18 vias is used, with a hole diameter of 0.38 mm. The calculated thermal resistance of this via array is approximately 7.7°C/W.Figure 11: TSSOP PCB LayoutTypically, these thermal vias use hole diameters of 0.4 mm or smaller to prevent solder wicking. If the SMT process requires smaller hole diameters, the number of vias should be increased to maintain a low overall thermal resistance as much as possible.In addition to vias located in the pad area, thermal vias are also provided in the outer area of the IC. In TSSOP packages, copper areas can extend beyond the ends of the package, providing an additional path for heat from the device through the top copper layer.The board surrounding the edges of QFN devices avoids using copper layers on top to absorb heat. Thermal vias must be used to dissipate heat to the inner or bottom layers of the PCB.Figure 12 shows the PCB layout for a small QFN (4 × 4 mm) device. In the exposed pad area, only nine thermal vias are accommodated. (See Figure 12) Therefore, the thermal performance of this PCB is not as good as that of the TSSOP package shown in Figure 11.Figure 12: QFN (4mmx4mm) Layout

Flip Chip QFN Package

The flip chip QFN (FCQFN) package is similar to the conventional QFN package, but the chip is directly connected to the board on the bottom of the device in a flip manner, rather than using bonding wires to connect to the package board. These pads can be placed on the backside of the power devices on the chip, so they are typically arranged in a long strip rather than small pads (see Figure 13).Figure 13: FCQFN PackageThese packages use multiple rows of copper bumps to bond to the lead frame (Figure 14).Figure 14: FCQFN StructureSmall vias can be placed within the pad area, similar to conventional QFN packages. In multilayer boards with power and ground layers, vias can directly connect these pads to various layers. In other cases, copper areas must be directly connected to the board to draw heat from the IC into larger copper areas.Figure 15: FCQFN PCB LayoutFigure 15 shows a power stage IC from MPS, the MP6540. This device has long power and ground pads, as well as three output pads. Note that this package is only 5mmx5mm.The copper area on the left side of the device is for power input. This larger copper area is directly connected to the two power pads of the device.The three output pads connect to the copper area on the right side of the device. Note that the copper area expands as much as possible after exiting the board. This allows heat to be effectively transferred from the board to the surrounding air.Also, note the several rows of small vias in the two pads on the right side of the device. These pads are all grounded, and a solid ground layer is placed on the back of the PCB. The diameter of these vias is 0.46 mm, with a drill hole diameter of 0.25 mm. The vias are small enough to fit within the pad area.In summary, to successfully implement PCB design using motor driver ICs, careful layout of the PCB is essential. Therefore, this article provides some practical suggestions that are expected to help PCB designers achieve good electrical and thermal performance of the PCB.Source: MPS

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