Article Overview
Today, this article mainly discusses how the commonly used DVFS method in the industry reduces power consumption, what type of power consumption is reduced, and why it can lower power consumption.
Main Purpose
Currently, under advanced processes, different chip manufacturers are pursuing low-power chip design for various reasons. Some manufacturers have certain requirements for power consumption and battery life in mobile products, while others have demands for heat dissipation and energy efficiency. There are also manufacturers who feel the need to keep up with others, even if they do not necessarily need it themselves.
Over the years, regardless of how hard chip engineers work or how much the processes improve, the principles for achieving low power consumption have not changed significantly. This is not due to a lack of effort from engineers; today we will discuss the relatively common DVFS.
Main Principle
Power consumption can mainly be divided into dynamic power and static power. Dynamic power can be expressed by a formula, primarily involving switching frequency and voltage. Static power is difficult to describe with a formula, but it is closely related to temperature and voltage. Therefore, if we can lower the voltage, both static and dynamic power consumption will be directly reduced. Furthermore, as power consumption decreases, temperature naturally drops, which can further reduce static power consumption. It is important to note that temperature has an exponential effect on leakage power consumption.
Among the two types of power consumption, dynamic power is the larger portion. From the formula for dynamic power, we can see that it is related not only to voltage but also to switching frequency. Thus, lowering the switching frequency can naturally reduce power consumption. However, it should be noted that simply lowering the frequency can only reduce power, not the power consumption required for the chip to complete a task. This is because the number of transitions required to perform the same task is fixed; when the chip’s operating frequency is lowered, the operating time will naturally increase, which is an important point to consider.
So why can DVFS reduce power consumption by lowering frequency? This needs to be understood from a different perspective. For example, if the CPU is continuously executing a workload that is not very heavy, but this workload needs to be executed for a certain duration, meaning the duration cannot change, then lowering the frequency becomes meaningful. Moreover, if the actual needs can still be met at a lower frequency, why would we need a higher voltage? We need to recall the relationship between voltage and frequency. Voltage determines the delay of the standard cell, and timing can be simply understood as the sum of the delays of the standard cells compared to frequency. Therefore, if the frequency decreases, what difference does it make if the sum of the delays of the standard cells increases a little? Thus, with the decrease in frequency, the voltage can also be lowered.
From the analysis above, it can be seen that DVFS involves changes in both voltage and frequency. Can we change just one of them? The answer is yes, but it is not recommended. For example, if we only dynamically adjust the frequency, what does that mean? It means that the current voltage can meet the timing requirements at all frequencies. Simply adjusting the frequency may not yield complete benefits and could even lead to negative outcomes, which would not be low power consumption but rather additional power consumption. Similarly, if we only adjust the voltage, it would not only be difficult to achieve power savings but could also increase power consumption and complicate the backend signoff process. In summary, DVFS should be a unified and coordinated process; focusing solely on one aspect is unlikely to achieve the desired results.
To be continued.