Low Power Design in Video Codec

This paper introduces three techniques: two-layer clock gating, skip mode, and a three-layer memory structure with a memory access unit, to optimize gate-level circuits and reduce power consumption in digital systems.

Two-layer Clock Gating

Among the various power optimization techniques proposed, clock gating is one of the most effective. It works by turning off the logic gates that insert clock units, thereby shutting down the circuit for a period. There are two types of clock gating: register-based and module-based. Figure 1 illustrates these two types of clock gating. If the RTL syntax follows the recommendations of EDA tools (such as design compilers), register-based clock gating will automatically insert clock gating units into all flip-flops. The clock gating unit includes latches and AND gates, which are used to reduce glitches and control the clock. Although convenient, register-based clock gating is not useful for developing complex designs due to syntax limitations, and adding clock gating to every register significantly increases circuit area. However, module-based clock gating uses enable signals to control whether the internal clock of each module is turned on or off. When the enable signal is high, the clock is passed to the module, allowing it to operate. All flip-flops within this module share the same clock gating unit. Since the clock gating unit itself consumes additional power, setting clock gating units for each module rather than for each register will also significantly reduce power consumption.

After weighing the trade-offs between reducing power consumption and area overhead, the paper proposes a two-layer clock gating scheme for video codecs. Figure 2 shows the two-layer clock gating scheme. First, the clock gating circuit is applied to each functional block (e.g., intra-frame prediction, motion estimation, discrete cosine transform, etc.) at the first level, as each block may take a variable number of cycles to process a partition of an image (such as LCU, CU, and PU). Additionally, the second level of clock gating circuits is applied to the modules within each functional block (such as state machines within the module). This two-layer clock gating approach significantly reduces both the area overhead and additional power consumption of the clock gating circuit compared to the register-based clock gating scheme.

Skip Mode

Many video coding standards define a “skip” mode to achieve better coding efficiency. For example, MPEG-4, H.264/AVC, H.265/HEVC, and H.266/VVC all provide skip modes to indicate that all coefficients after LCU transformation quantization are zero, thus the dequantization inverse transformation unit does not need to perform any additional calculations. Furthermore, when the filtering strength of the deblocking filter in the H.264/AVC decoder is at its minimum, the deblocking filter does not need to perform any calculations. By using these modes, we can bypass all operations and directly forward the raw data to the output memory. In other words, the processing cycles of the functional blocks entering skip mode can be further shortened, allowing us to turn off their clocks more frequently, thereby reducing more power overhead.

Combined Application Effects:

Three-layer Memory Structure with Memory Access Unit

Internal memory (such as SRAM) and external memory (such as SDRAM) are common and important storage units in video codecs. The paper researched designs a memory hierarchy scheme to access memory more efficiently and reduce its energy consumption. The principle of the three-layer memory hierarchy technology is to only keep the required data for the currently processing LCU in the corresponding internal memory, while storing the reference data for subsequent partitions in external memory. This technique is particularly useful for video codecs, as most video encoding algorithms predict the current partition’s data by referencing pixels from its adjacent partitions. Therefore, entire rows of these reference data must typically be stored in the image.

Additionally, to access external memory more efficiently, the paper implements a memory access unit (MAU) to transfer reference pixels of functional blocks within the video codec. Figure 6 illustrates this technology. The MAU can access the external memory of the video codec more efficiently for two reasons. First, many functional blocks in the video codec process the current partition by referencing adjacent LCUs, which are typically stored in external memory. For example, motion estimation, intra-frame prediction, and entropy encoder in the H.264/AVC encoder must access adjacent blocks. The MAU can simplify the access for these functional blocks. The second reason is that video encoders do not output compressed data periodically, which can lead to excessive memory traffic. The MAU can reduce external memory traffic by using local buffers. In summary, the MAU acts as both a FIFO and a circular buffer.

Energy Saving Effects:

2.4 Comprehensive Effects

Metric	Original Power Consumption	Optimized Power Consumption	Reduction
Average Power Consumption of H.264 Decoder	38.39mW	21.2mW	45%↓
Average Power Consumption of H.264 Encoder	41.6mW	23.6mW	43%↓
Peak Power Consumption of Decoder	734mW	404mW	45%↓

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