In the early 1980s, Professor David Patterson from the University of California, Berkeley, and Professor John Hennessy from Stanford University led teams that proposed the concept of Reduced Instruction Set Computing (RISC). The fundamental idea of RISC is to simplify the instruction set, making processor design simpler and more efficient.
In 2010, Professor Krste Asanović from the University of California, Berkeley, and his team launched the RISC-V project, aiming to design a new, open instruction set architecture that meets the needs of modern computing. In 2014, the team released the initial specifications for RISC-V, including basic instruction sets for 32-bit and 64-bit architectures. The release of these specifications marked the official entry of RISC-V as an open-source instruction set architecture into the public eye.
Krste Asanović, Chief Architect of the RISC-V International Foundation, Chief Architect of SiFive, and Honorary Professor at the Graduate School of the University of California, Berkeley
On July 17, Krste Asanović delivered a speech titled “The State of Unity” at the 2025 RISC-V China Summit held in Shanghai. He systematically elaborated on the extensive applications of RISC-V in the embedded field, application processors, and AI accelerators, emphasizing its future potential as an open standard instruction set architecture (ISA) and outlining the blueprint for RISC-V’s development in vertical fields.
The Current Status and Achievements of RISC-V
Asanović pointed out that RISC-V has established a solid foundation in the embedded field, with chip shipments reaching “tens of billions or even hundreds of billions”. At the same time, its popularity in the application processor field is accelerating, with its open standard features and modular design making it an ideal choice for emerging AI accelerators.
“The most exciting progress for RISC-V is its deployment in the AI field,” he emphasized. The general computing model of RISC-V supports a balance of scalar, vector, and matrix capabilities (such as the Zvfbfa and Zvfofp8min proposals), allowing the same core to run both non-AI and AI tasks, thereby simplifying software development, reducing latency, and improving hardware utilization.
Experimental data shows that hardware platforms based on RISC-V can efficiently run early AI models, and the cost of adapting new models is low.
He also mentioned that the flexibility and scalability of RISC-V allow it to meet a wide range of needs, from low-power microcontrollers to high-performance computing. Through modular design, developers can flexibly combine instruction set components to meet customized needs in different markets. This “simple, flexible, and open” characteristic allows RISC-V’s application scope to far exceed that of other instruction set architectures.
Expansion in Vertical Fields and Ecosystem Building
Asanović stated that RISC-V is entering multiple vertical fields (such as automotive, industrial control, and the Internet of Things), but success in each field relies not only on a single technological breakthrough but also on the collaborative construction of ecosystems across the industry chain. “We need to fill the gaps in instruction set or software support while maintaining the coherence of the overall ISA design.”
1.Microcontrollers and the Automotive Field
The RVM profile for microcontrollers (draft RVM23) has been initiated, and automotive-grade MCU standards will be introduced in the future. Asanović emphasized that by empowering microcontrollers with open-source standards, RISC-V will further penetrate high-reliability scenarios such as automotive electronics.
2. AI and Matrix Extensions
Support for AI is a core direction for RISC-V’s future development. Currently, RISC-V vector extensions (RVV) support data types such as BF16 (Zvfbfa) and OFP8 (Zvfofp8min), and various matrix extension schemes (such as Zvbdot, Separate-Matrix, Vector-Matrix) enhance AI computing efficiency. Asanović revealed that matrix extension technology will become the most active part of RISC-V standard development.
3. Security and Memory Protection
To address security challenges, RISC-V is developing several security extensions, including SPMP (Second Level Memory Protection), CHERI (Capability Hardware Enhancement), and Lightweight Memory Tagging, to support real-time operating systems and high-security application scenarios.
The Standardization Process and Roadmap of RISC-V
Asanović detailed the standardization progress of RISC-V:
1.RVA23: Released in October last year, RVA23 is a milestone version of the RISC-V application architecture, containing key features such as virtualization monitoring. Although hardware implementation will take time, its standardization lays the foundation for ecosystem compatibility.
2.RVA30 and Progressive Updates: The next major version, RVA30, is planned for release in 2030 and will introduce more mandatory features. Before that, RISC-V will gradually improve features through minor versions (such as RVA23.1, RVA23.2) to accumulate experience for the release of RVA30.
3.Long Instructions and Code Optimization: RISC-V has supported variable-length instructions (16-bit compressed instructions and instructions longer than 32 bits) since its design inception to reduce code size and enhance performance. This feature is particularly important in AI and complex data processing scenarios.
Asanović revealed that the hardware solutions for RVA23 will be implemented within the year, while the next generation RVA30 is planned for release in 2030, focusing on longer instruction formats (>32 bits) and support for new data types to meet the growing demand for computing power.
The Future Vision of Open Standards
Asanović emphasized that the success of RISC-V stems from its openness: “More and more industry participants realize that RISC-V will become the mainstream ISA of the future.” He pointed out that although the timelines for different fields to become mainstream vary, the open standard characteristics of RISC-V enable it to reuse technology across fields, promoting the collaborative evolution of the entire ecosystem.
In addition, the deep collaboration between RISC-V and operating systems such as Linux and Android further consolidates its competitiveness in general computing and AI fields. Asanović stated: “We are working with partners to ensure that the RISC-V software ecosystem can match hardware innovations, providing seamless support for developers.”
In conclusion, Asanović summarized that RISC-V has moved from “concept” to “practice”, with its foundational components in place and functioning well. In the future, RISC-V will continue to drive technological innovation and industrial implementation by focusing on vertical fields and improving ecosystem shortcomings. “RISC-V is not just an instruction set; it is an open platform connecting global developers and industries,” he said.