Yesterday, a dedicated fan messaged me asking if I could explain some considerations for GMSL routing. I said I would update it once I returned from my business trip to Israel. Of course, many enthusiastic fans later shared their thoughts, and I will answer and share with everyone one by one. This article mainly shares some considerations regarding GMSL routing from Maxim’s manual. Don’t forget to like and follow after reading, everyone!
Edit
The layout design rules for GMSL2 are as follows, everyone should take notes:
1. Route the serial link trace as a microstrip on the top layer or as a stripline in a middle layer (if EMI/EMC is a concern). Route the serial link trace (GMSL) as a microstrip on the top layer or a stripline in the middle layer (if EMI/EMC is a concern).
Edit
(GMSL2 routing on layer L3)
Edit
(GMSL2 routing on layer L3)
Currently, I often find that placing GMSL routing on inner layers is better.
2. Use 100-ohm differential or 50-ohm single-ended trace routing with impedance control (±10%). Use 100-ohm differential or 50-ohm single-ended trace routing with impedance control (±10%).
Edit
3. Minimize impedance discontinuities by using proven design and simulation practices. (Minimize impedance discontinuities by using proven design and simulation practices). This mainly requires that the GMSL trace should not have crossing splits.
4. Place IC as close as possible to the connectors to minimize trace length. Traces should be less than 2 inches (5 cm) to meet the GMSL PCB channel specification. (Place IC as close as possible to the connectors to minimize trace length. Traces should be less than 2 inches (5 cm) to meet the GML PCB channel specification.)
Edit
(Schematic and Layout example for single-ended (COAX) operation)
Edit
(Schematic and layout example for shielded twisted pair (STP) operation)
Edit
Regarding the requirement that GMSL routing should be less than 2 inches, I have done simulation comparisons. In fact, as long as the insertion loss (IL) on your channel meets the GMSL limit curve requirements, it is acceptable even if the GMSL routing exceeds a little. Of course, if the GMSL routing can be kept shorter, it is still advisable to maintain that.
5. Minimize vias. If vias are required, eliminate via stubs by using back-drilled vias, and add ground transition vias next to signal vias. (Minimize vias. If vias are required, eliminate via stubs by using back-drilled vias, and add ground transition vias next to signal vias.)
From a cost perspective, we can reduce via stubs by placing interfaces and chips on different layers; it is not necessary to optimize this with back-drilling. Additionally, we can remove non-functional pads of the via connector, enlarge the solder pad size, and remove non-functional pads of the signal via on different layers. These three optimization methods are generally sufficient. Currently, almost all major companies’ projects are focused on cost reduction and efficiency improvement. If you increase project costs at this time, wouldn’t that cause your department’s PM to have a talk with you?
Edit
6. Place AC coupling capacitors on the top layer as close to the IC as possible (within 500 mils ensures it is less than 0.5 UI from the transmitter). Route signals differentially to the AC coupling capacitors, even in COAX mode. Ensure 100-ohm impedance and length matching to the AC capacitors. (Place AC coupling capacitors on the top layer as close to the IC as possible (within 500 mils ensures it is less than 0.5 UI from the transmitter). Route signals differentially to the AC coupling capacitors, even in COAX mode. Ensure 100-ohm impedance and length matching to the AC capacitors.)
Edit
Edit
In practice, we also place this capacitor close to the IC, so this generally meets the requirements mentioned in the manual.
7. In COAX mode, terminate the SION trace with an AC coupling capacitor and a 50-ohm resistor to ground.
Edit
8. In STP mode, ensure length matching and consistent coupling distance between traces. (In STP mode, ensure length matching and consistent coupling distance between traces.)
9. Eliminate stubs by placing component pads directly on the high-speed trace, including line faults, POC, and ESD components. (Eliminate stubs by placing component pads directly on the high-speed trace, including line faults, POC, and ESD components.)
Edit
10. Use cutouts in the reference layer under the pads of components on the high-speed trace. The size of these cutouts depends on the specific PCB stackup. For example, for Maxim Evkits, the cutouts are 1.35X the pad size. (Use cutouts in the reference layer under the pads of components on the high-speed trace. The size of these cutouts depends on the specific PCB stackup. For example, for Maxim Evkits, the cutouts are 1.35X the pad size, this is also a design experience value, and it should be analyzed based on your specific board situation.)
Edit
Taking a 10-layer board as an example, the pads on the AC capacitor side are hollowed out on the adjacent GND layer, and the L8 layer has supplemented the GND plane below the hollowed-out area.
Edit
The hollowing of the reference plane here includes two parts:
1. Hollowing for the POC inductor circuit.
2. Hollowing of the reference plane for the device pads in GMSL routing.
Regarding the size of this hollowing, I mentioned it in my previous explanation about POC, interested friends can refer to previous articles.
Marin’s Summary on PCB POC Circuit Layout Design
11. Follow connector vendor layout footprint recommendations. (Follow connector vendor layout footprint recommendations.) This mainly states that we need to refer to some recommendations provided by the connector vendor during layout.
12. For through-hole connectors, use topside mounting of IC and bottom-side mounting of the connector to minimize connector pin stubs to improve return loss. (For through-hole connectors, use topside mounting of IC and bottom-side mounting of the connector to minimize connector pin stubs to improve return loss.)
Edit
13. Avoid 90-degree bends on high-speed lines. (Avoid 90-degree bends on high-speed lines.)
Our GMSL routing cannot have 90-degree angles; currently, I optimize GMSL routing with arcs.
Edit
14. Maintain a continuous reference plane under high-speed traces – no split ground or power planes under the serial link trace, except for ground cutouts. (Maintain a continuous reference plane under high-speed traces – no split ground or power planes under the serial link trace, except for ground cutouts.)
This mainly states that our GMSL routing should have a complete reference ground plane, and routing should not have crossing splits.
15. ESD protection should be placed near the RF connector if required for the application (and POC is not used). (If required for the application, ESD protection should be placed near the RF connector (POC is not used).)
Regarding the placement of ESD, I will separately explain in a future article whether it is better to place it near the interface or near the IC chip. I won’t elaborate here because it requires a lot of explanation, and if I talk too much, some friends might get annoyed, which would not be good for their reading mood, and I feel sorry for that. So let’s talk about it next time when I have time.
Edit
16. Use an array of ground vias in the exposed ground pad (EP) for thermal management. (Use an array of ground vias in the exposed ground pad (EP) for thermal management.)
This mainly states that remember to add more GND vias for the thermal pads near the IC chip.
Edit
17. High-speed video interfaces (HDMI, OLDI, DP, eDP, DSI, CSI CPHY, CSI DPHY) and other high-speed interfaces (such as RGMII, SPI) all have their own layout requirements and impedance specifications, length matching tolerances, and maximum trace lengths. Follow the guidance given in each specification. (High-speed video interfaces (HDMI, OLDI, DP, eDP, DSI, CSI CPHY, CSI DPHY) and other high-speed interfaces (such as RGMII, SPI) all have their own layout requirements and impedance specifications, length matching tolerances, and maximum trace lengths. Follow the guidance given in each specification.)
• Maintain pair-to-pair and signal-to-signal distances for high-speed signals to reduce crosstalk.
A. Differential pair-to-pair distance at least 2x separation away.
B. Single-ended signals at least 3x trace width away or isolate on a different layer.
That’s all for this issue. In the next article, we will further analyze through an actual simulation case.
Edit
——– Disclaimer: This article belongs to the original work of the author. If reprinted, please indicate the source! The design rules regarding GMSL2 are derived from Maxim’s chip manual (GMSL2 Hardware Design Guide Revision 17.2).