The switching node of a switching regulator or power converter circuit is a critical conduction path that requires special attention during PCB layout. This circuit node connects one or more power semiconductor switches (such as MOSFETs or diodes) to magnetic energy storage devices (such as inductors or transformer windings). Its switching signals contain rapidly switching dV/dt voltages and dI/dt currents, which can easily couple into surrounding circuits and cause noise issues, potentially leading to the PCB and system failing to meet stringent electromagnetic compatibility (EMC) requirements.
This article will introduce the most basic switching node waveforms to help you understand how to determine the appropriate switching (SW) node trace size during PCB routing, and to understand the near-field coupling effects generated by electric fields (E-field) and magnetic fields (H-field) at the switching node.
Switching Node Waveform
Before starting the PCB design of these critical traces, it is essential to understand the current and voltage waveforms at the switching node. It is particularly important to review and understand the switching voltage, time-varying current, and switching frequency waveforms before layout.
We will illustrate this using the MPS buck converter MPQ4430 as an example (see Figure 1). The buck converter MPQ4430 integrates both high-side and low-side FETs and can provide up to 3.5A of load current.
Figure 1: Example of MPQ4430 Buck Converter
In this example, we used MPS’s DC/DC online designer tool to design the MPQ4430 regulator to step down from 12V to 3.3V while providing a maximum load current of 3A. The switching node in Figure 1 is marked in red as VSW. Note that “VSW” and “the SW node” are interchangeable terms referring to the switching node.
Figure 2 shows the switching voltage waveform and inductor current waveform measured at its switching node. The voltage waveform switches between 12V and slightly below 0V at a frequency of 500kHz, but the rise/fall times are within very low nanoseconds. Such a high dV/dt generates a strong electric field (E-field) noise spectrum reaching tens to hundreds of megahertz.
Figure 2: Switching Node Waveform of Buck Converter
Since the buck converter operates in continuous conduction mode, the inductor current is always positive and never reaches 0A. The current rises to about 3.4A during the on period of the buck converter and drops to about 2.6A during the off cycle. An average of 3A current is supplied to the load. The inductor prevents rapid changes in current, so the current waveform does not have steep transitions like the switching voltage. Although dI/dt is not very large, ripple current still exists at a switching frequency of 500kHz, generating a strong time-varying magnetic field (H-field). This magnetic field can pose potential problems for nearby circuits sensitive to this frequency range.
Minimize the Length of the Switching Node Trace
The switching node trace needs to carry relatively large time-varying currents over short distances. The inductor should be placed very close to the regulator’s SW pin. The shorter the trace, the less coupling there will be from the high-frequency electric field generated by the high dV/dt waveform and the low-frequency magnetic field from the inductor’s ripple current.
Figure 3 shows an example of routing the switching node, where the inductor is placed close to the regulator. When designing the PCB layout, pay attention to leaving a small area between the converter and the inductor for other components that must connect to the switching node (such as small bootstrap capacitors). However, the principle of layout is to minimize the length of the SW trace as much as possible.
Figure 3 shows that the placement principle for the bootstrap capacitor is to orient its longest side perpendicular to the SW trace. This minimizes unnecessary distance between the SW pin and the inductor. Although the capacitor slightly pushes the inductor away, a super short trace of about 3mm to 4mm can still be achieved. The specific length of the VSW trace depends on the application and component size and may be longer than this example in some cases.
Determine SW Node Trace Size to Meet Current Requirements
Typically, the trace from the regulator’s SW pin to the input side of the inductor should be wider than other signal traces on the PCB. We recommend using wide traces or copper pours that meet the following requirements:
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Copper thickness and trace width should be sufficient to meet current demands.
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Trace length should be as short as possible to minimize near-field coupling with other circuits.
The width of the SW node trace is crucial for handling the required inductor current. In the aforementioned buck converter example, the average current supplied to the inductor is the same as the average output current (3A). Design engineers should first specify the maximum current conditions and then use that to estimate the trace width of the SW node.
In our design example, assume a 4-layer PCB uses 1 ounce of copper on the top layer, bottom layer, and inner layers (see Figure 4). The switching regulator circuit is routed on the top layer, and the ground (GND) return plane is positioned 9.26 mils (approximately 10 mils) below the top layer. We can determine the size of current-carrying conductors using many available calculation tools. These tools can be found in PCB CAD software or on PCB manufacturers’ websites.
Figure 4: 4-Layer Stack Used in 3A Buck Converter
If the maximum load designed is 3A and it is required to control the PCB’s temperature rise within 10°C, calculations show that using this 4-layer stack, a conductor width of 50 mils should be able to carry nearly 3.5A of current. Therefore, in this design, a switching node trace width of 50 mils is a good choice, providing a margin above the maximum load of 3A. Of course, different trade-offs can be made based on the allowable temperature rise of the specific PCB. While it is common for trace sizes to be the same width as inductor pads, this example shows that narrower traces can still fully meet current and thermal requirements.
Note that the calculation of current conductor sizes should follow the latest IPC2152 standard, not the older IPC2221 version. This is particularly important for multilayer PCBs. Calculations based on IPC2152 are more accurate and consider many factors such as PCB thickness, PCB thermal conductivity, trace thickness, and the distance from the trace to the copper plane.
Electric and Magnetic Fields of SW Node
The switching node trace consists of PCB traces above the reference plane and can be viewed as a very short version of a microstrip line, especially at high frequencies. The impedance of the microstrip line is controllable and is used for transmitting digital, high-speed analog, and radio frequency (RF) signals in high-speed transmission line applications. Although the expected signals conducted by the switching node and microstrip transmission line differ in application, their geometries exhibit similar characteristics for time-varying electric and magnetic fields.
Figure 5 shows the electric and magnetic fields generated by the switching voltage and time-varying current on the SW trace. The SW trace (width w) is positioned at a height h above the return plane. Electric field lines extend from the top, bottom, and sides of the SW trace. The strongest electric field (especially at high frequencies) is concentrated at the bottom and edges of the trace closest to the return plane.
Figure 5: Electric and Magnetic Fields of Switching Node
At high frequencies, currents appear where electric field lines terminate at the return plane. To better control the electric field and reduce parasitic near-field coupling, the distance (h) between the return plane and the SW trace should be minimized, and the distance between the SW trace and surrounding circuits should be maximized.
The ripple current in the SW trace generates a time-varying magnetic field around the trace. The magnetic flux from the magnetic field can couple into nearby sensitive circuits through mutual inductance. Similar to the electric field, the best way to limit the magnetic field is to minimize h, bringing the return plane as close to the SW trace as possible while increasing the distance between the SW trace and surrounding circuits. Placing a dedicated GND return plane close to the SW node will provide good magnetic field suppression capability.
Conclusion
For any switching regulator or power converter circuit, the layout of the SW node must be taken seriously. Understanding the SW node waveforms, determining reasonable SW trace sizes, and developing strategies to minimize near-field coupling are all crucial.
First, we must fully understand the switching voltage waveform, current waveform, and switching frequency. Then, determine the SW trace width based on maximum current requirements and minimize the length of the SW trace as much as possible. Finally, leave enough spacing between the SW node and surrounding ICs and circuits to minimize near-field coupling. When using multilayer PCB stacks, always place the GND return plane directly beneath the SW trace and ensure the trace is as close to the GND plane as possible. This will further reduce near-field coupling from the electric and magnetic fields generated by the SW node.
Following the principles outlined above when designing PCB layouts will help achieve better EMC design!