In the post-Moore’s Law era, the paradigm shift in computing power is gradually moving RISC-V from edge scenarios to mainstream architecture due to its open, modular, and scalable characteristics. In this global competition of “architecture reconstruction,” Infineon is quietly playing a role as a “steady yet transformative” player: neither rushing to replace ARM as the main platform nor avoiding to reserve strategic space for RISC-V in emerging fields such as automotive electronics, embedded security, and edge AI.
At the 5th RISC-V China Summit, Thomas Schneid, head of software partner ecosystem management at Infineon, and Linda Liu, senior marketing manager at Infineon, delivered a speech titled “Accelerating the Construction of the Automotive RISC-V Ecosystem Together to Drive Smart Mobility Development,” sharing Infineon’s RISC-V strategy comprehensively.
1. Post-Moore’s Law Era: The Background of RISC-V’s Rise
Thomas Schneid pointed out that the slowdown of Moore’s Law and the fragmentation of computing power demand are driving chip architecture towards heterogeneity, specialization, and open-source development. RISC-V embodies the following strategic values in this trend: an open architecture brings autonomy and control, reduces dependence on licensed IP, and a modular ISA is conducive to tailored adaptations for differentiated scenarios; global industry collaboration is promoting increasingly mature standards.
Against this backdrop, Infineon systematically deploys RISC-V as a core architectural option for safety control, functional co-processing, and embedded intelligence modules, gradually forming a “heterogeneous collaboration” strategy coexisting with ARM.
2. Strategic Layout: Coexistence from Auxiliary Controllers to Main Cores
He introduced that Infineon is orderly introducing RISC-V across multiple product lines, reflecting a layered advancement strategy of “from edge embedding → system collaboration → ecosystem integration”:
1. Safety Subsystem: RISC-V as the Trusted Core in Automotive MCUs
In its next-generation AURIX™ TC4x automotive MCU, Infineon has embedded RISC-V as the safety control core (Safety Island) for the first time, undertaking the following functions: secure boot, safety state monitoring, fault detection, anomaly isolation, and collaborative communication with the main ARM core, enhancing the functional safety level (ASIL-D).
Compared to the closed ARM cores, the autonomous and controllable RISC-V cores are more suitable for assuming the role of “trusted root,” facilitating chip manufacturers to customize security mechanisms and build differentiated solutions.
2. AI Acceleration and Programmable Computing: Collaboration with ARM Rather than Replacement
Infineon is deploying RISC-V as a dedicated co-processor/computing unit in edge AI, sensor processors, and smart power control, working in collaboration with the main ARM core. For example, RISC-V vector processing units for edge machine learning inference and custom RISC-V cores in real-time signal processing, featuring ultra-low power consumption and a streamlined instruction set, support field-reconfigurable logic (eFPGA) combined with RISC-V to enhance flexibility.
Thus, it can be seen that Infineon regards RISC-V as a “computing patch,” achieving functional enhancement and programmable expansion of traditional MCUs.
3. Ecosystem Construction: From Single-Core Architecture to System Platform
Thomas Schneid stated that Infineon recognizes that the key to RISC-V’s success lies not only in the performance of the cores but also in the completeness of the toolchain, software ecosystem, and standard interfaces. Therefore, it is focusing on the following aspects:
1. Supporting mainstream RISC-V toolchains: such as GCC/LLVM, OpenOCD debuggers, etc.;
2. Building a complete development platform: launching development boards/evaluation kits containing RISC-V cores for universities, developers, and partners;
3. Promoting ISO 26262 safety certification: incorporating RISC-V cores into the functional safety certification system to broaden its automotive application pathways.
At the same time, Infineon collaborates with RISC-V IP vendors such as SiFive and Codasip to optimize the deployment efficiency of RISC-V cores in its chip architecture.
4. “Complementary” Rather than “Disruptive”: Infineon’s Pragmatic Choice
Unlike some vendors who loudly claim to “fully embrace RISC-V,” Infineon prefers a “steady integration”:
| Strategic Choice | Content |
|---|
| Coexistence with ARM | Not directly replacing ARM Cortex-A/M cores, retaining the existing software ecosystem |
| Key Breakthroughs | RISC-V used in auxiliary, safety, and AI subsystems, building heterogeneous collaboration |
| Smooth Transition | Self-developed RISC-V subsystems have good interface compatibility, adapting to existing toolchains |
| Industry Collaboration | Participating in the RISC-V International Foundation, promoting the development of industry standards |
This strategy reflects its long-term thinking towards future architectural evolution: not an immediate revolution, but leaving room and flexibility for change.
The Integration Template of RISC-V with the European Industrial System
Infineon’s layout in RISC-V is not only a response to technological trends but also a concrete practice of Europe’s autonomous semiconductor strategy. Especially in the context of rising global supply chain uncertainties and tightening export controls, RISC-V is becoming a key support for Europe’s industrial “autonomy, openness, and security.”
In the future, RISC-V is expected to become the strategic foundation of Infineon’s chip platform in the following areas: functional safety cores for smart vehicles, AI programmable units for industrial edge, and ultra-low power embedded processors for distributed sensing.
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