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On July 16, 2025, during a visit to the “5th RISC-V China Summit” exhibition, a particularly crowded booth caught the attention of reporters from the Nonferrous Network. It turned out to be a company called “ChaoRui Technology,” whose latest high-performance 8-core 64-bit RISC-V microprocessor UR-DP1000 has garnered widespread attention in the industry.
So, what kind of company is ChaoRui Technology? Why are their products so attractive? With these questions in mind, the reporter listened to the speech titled “UR-DP1000: High-Performance 8-Core 64-Bit RISC-V Microprocessor” by Jiang Jiang, Executive President and CTO of ChaoRui Technology, at the “High-Performance Computing Sub-Forum” on July 18.
According to Jiang Jiang’s introduction, ChaoRui Technology was established in 2021, headquartered in Zhangjiang, Shanghai, with R&D centers in Changsha and Wuxi. The company focuses on developing high-performance processor core IP and multi-core microprocessor (CPU) chip products based on the RISC-V “Open” Instruction Set Architecture (ISA) standard, widely covering mainstream application scenarios from “cloud-edge-end”.
ChaoRui Technology boasts a top-notch microprocessor chip design team from national-level processor R&D institutions and leading companies in the industry, capable of providing high-performance microprocessor chip products that have been mass-produced and silicon-validated high-performance processor core IP, along with an efficient and comprehensive software toolchain.
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Processor Core Layout: From UR-CP100 to UR-CP300
Regarding the company’s latest developments, Jiang Jiang revealed: “In the research and development of processor cores, ChaoRui Technology continues to advance along three technical routes focusing on high performance, high reliability, and high energy efficiency, among which the high-performance processor core UR-CP series has formed a complete product iteration.”
Specifically, the company’s first-generation UR-CP100 has achieved RVA2 standard compatibility, benchmarking against ARM A76, with a measured performance of 10.4 points; the second-generation UR-CP200 has improved performance to 13 points, directly competing with the ARM A78 architecture; the third-generation product currently under development is planned for official release in the first quarter of next year, with a performance target of 16 points to catch up with the ARM N2 architecture.
Regarding the processor core, Jiang Jiang further emphasized: “Our high-performance processor core UR-CP series has achieved continuous iteration, with each generation showing significant improvements in instruction set support, microarchitecture optimization, and performance.”
The main improvements are reflected in the following aspects:
First Generation UR-CP100 Based on the RV64GCBHX instruction set, compliant with RVA22 specifications, it adopts an out-of-order 4-issue 12-stage pipeline design, supports virtualization extensions H and private extensions X, allows for configurable multi-level Cache, and integrates an advanced branch prediction mechanism, achieving a measured SPECint2006 score of 10.4/GHz. Its modular design allows for 1-8 cores to form a compute cluster, sharing L3 Cache and supporting the CHI/ACE coherence bus, suitable for flexible high-performance scenarios.
Second Generation UR-CP200 Further enhances vector processing capabilities under the RVA23 specification, adding over 70 enhanced instructions, supporting 256-bit wide RV Vector 1.0, and introducing the Advanced Interrupt Architecture (AIA). Its out-of-order 6-issue design drives a 20-25% performance increase, achieving SPECint2006 scores of 13/GHz, directly competing with ARM Cortex-A78.
Third Generation UR-CP300 Continues RVA23 compatibility, deeply optimizing the 6-issue microarchitecture for server-level workloads, supporting configurable vector widths and AIA extensions, with expected performance exceeding 16 points, a 20-25% improvement over the second generation, targeting ARM Neoverse N2, with plans for IP release in the first quarter of 2026.
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CPU Product Layout: From Edge Computing to Server-Level Product Lines
In terms of CPU product layout, ChaoRui Technology has established three differentiated product lines: high-end edge computing chips for unmanned systems designed with 2-4 cores and integrated AI acceleration capabilities; the desktop-level CPU product UR-DP1000 has completed tape-out and is entering mass delivery; the server-level product line is developing the SP2000 based on the third-generation core, a 32-core single-die high-performance chip expected to start tape-out in the second half of next year.
During the conference, Jiang Jiang focused on introducing the UR-DP1000 high-performance microprocessor chip, its performance, and the system software ecosystem and application scenarios surrounding the UR-DP1000.
The UR-DP1000 high-performance microprocessor chip is built on 8 UR-CP100 processor cores, using a 12nm process, aimed at efficient computing and diverse application scenarios. The chip exhibits excellent single-core performance, achieving SPECint2006 scores of 10.4/GHz and SPECfp2006 scores of 12.0/GHz, with a working frequency of 2.0-2.3GHz and TDP controlled at 30W, demonstrating outstanding energy efficiency. Its modular design integrates 2 clusters, each containing 4 cores and sharing 4MB L3 Cache, while a global 16MB LLC further optimizes multi-core data collaboration, supporting the RV64GCBHX instruction set and virtualization extensions to meet high-performance computing needs.
In terms of SoC architecture, the UR-DP1000 integrates dual-channel DDR4-3200 (supporting ECC), 24 lane PCIe 4.0 interfaces, and rich peripherals through Cache coherent NoC. Its physical design adopts FC-BGA packaging, with a die size of 12.8mm×12.8mm, and full-chip DFT testing ensures mass production reliability. After tape-out in March 2024, rapid adaptation to systems like Ubuntu will validate the maturity of hardware-software collaboration.
In terms of ecosystem development, the software ecosystem of the UR-DP1000 covers mainstream open-source toolchains and operating systems, supporting GCC/LLVM optimized compilation, Linux distributions, and domestic systems, achieving low overhead KVM virtualization (~3%).
Meanwhile, in terms of hardware compatibility, the UR-DP1000 has been adapted to domestic GPUs and accelerator cards such as XinDong and XinTong, promoting the implementation of fully domestic solutions.
Jiang Jiang revealed: “Currently, the UR-DP1000 has been applied in mATX/mini-ITX motherboard designs, supporting edge computing all-in-one machines, RISC-V compilation clusters, and industrial control fields, extending to specialized scenarios such as automotive, demonstrating flexible deployment capabilities.”
Therefore, the market development prospects of SI/PI simulation tools are closely related to the technological trends and market demands in the electronic design field. As the complexity of high-speed digital design, chip packaging, and system-level design increases, the market demand for related tools continues to grow.
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