Horizon Technology’s RISC-V Breakthrough Strategy: Full-Stack Collaboration from Toolchain to System-Level Platform
As RISC-V transitions from an “alternative option” to a “mainstream architecture” globally, the response from the Chinese market is particularly crucial. As one of the few domestic companies covering everything from chip-level EDA, system-level EDA to high-performance IP, at the 5th RISC-V China Summit, Wu Xiaozhong, Vice President of Horizon Technology, stated that Horizon Technology is injecting “engineering capabilities” into the RISC-V industrial ecosystem with a set of self-controlled, collaboratively integrated product systems. This article will delve into its strategic positioning, product solutions, and industrial logic related to RISC-V.
1. Small Industries Supporting Large Industries: The Era Task of Domestic EDA
As Wu Xiaozhong pointed out, although EDA has a market scale of only tens of billions of dollars, it serves as the “digital foundation” for semiconductor design, amplifying the support for a digital economy worth tens of trillions. In recent years, the intensification of the Sino-U.S. technological competition has further made “de-Americanization of EDA” an industry consensus. Particularly, under the U.S. 2023 “New Policy 1202”, advanced process design is forced to choose between the “big three” and domestic options; the 2024 “Whitelist Mechanism” and OSAT transfer requirements accelerate the risk of tool supply interruptions.
By 2025, control over core EDA tools remains a critical bottleneck hindering China’s high-end chip design. Against this backdrop, Horizon Technology positions RISC-V as a key scenario for integrating and verifying self-developed EDA and IP capabilities, reflecting its technical ambitions and carrying the important mission of promoting the “localization” of the RISC-V ecosystem.
2. RISC-V Strategic Positioning: Dual Role in Verification Scenarios
He noted that Horizon Technology does not view RISC-V merely as an IP business but as a touchstone and collaborative hub for maturing domestic EDA toolchain capabilities. In its overall solution, the RISC-V model is widely used for two main purposes:
1. Architecture Verification and Hardware-Software Collaborative Development Platform — Horizon provides self-developed RISC-V models for customers to explore architecture and pre-develop software in the early stages; if customers already have their own models, they can be seamlessly integrated into the virtual prototype platform (V-Bilder + vSpace); thus achieving an integrated path from architecture analysis → software debugging → simulation verification, helping RISC-V developers shorten development cycles.
2. Verification Platform Standard Scenario Adapters — Horizon has built UVHP, UVHS, and other hardware simulation/prototyping platforms supporting capacities from tens of millions to billions of gates, which are naturally compatible with RISC-V processor architectures, becoming efficient verification toolchains for deploying RISC-V cores like Xuantie and Kunming Lake;
In a case study, Horizon collaborated with Pingtouge to create a virtual prototype environment with speeds of 50MHz (single core) and 12MHz (inter-chip), providing a foundation for the early development of domestic RISC-V high-performance cores.
This strategy positions RISC-V not just as a “usage scenario” but as a “central node” in Horizon’s construction of a full-stack tool ecosystem.
3. Technical Depth: Complete EDA Coverage from DFT to Advanced Packaging
He stated that Horizon Technology’s core advantage lies in its EDA matrix that spans the entire chip design process. In supporting the landing of RISC-V SoCs, the key supports it provides include:
| Module | Support Value for RISC-V Development |
|---|---|
| Functional Verification Platform (UVHP / UVHS) | Supports hardware simulation, software co-debugging, and inter-chip communication verification for RISC-V SoCs |
| Virtual Prototype Platform (vSpace) | Provides a fully simulated RISC-V execution environment, compatible with customer-customized cores or self-developed cores |
| DFT Full Process Platform | Covers boundary scan, BIST, ATPG, diagnostics, and adapts to advanced process yield analysis |
| System-Level EDA (PCB + Packaging) | Supports RISC-V multi-chip integration and packaging base design, validating millions of pin-level scales |
| High-Performance IP Modules | Provides high-speed Ethernet, DDR, and other interface IPs to meet RISC-V SoC design needs |
It is worth noting that Horizon has achieved diagnostic positioning capabilities that are “more accurate than mainstream international tools” in DFT tools, indicating that its toolchain is no longer just a “domestic alternative” but possesses a technical foundation to challenge high-end markets.
4. Industrial Model: Diverse Verification Scenarios Supporting Ecological Closure
Horizon’s RISC-V strategy goes beyond being a “tool provider” and deeply participates in the verification and optimization of multiple real projects:
Kunming Lake Project Case: Addressing multi-core communication and high-performance debugging challenges; Horizon achieved efficient performance through multi-board cascading + timing segmentation; meeting EMU-level debug requirements.
Pingtouge Xuantie Project Case: Virtual prototype speeds of 50MHz (single core)/12MHz (inter-chip); achieving dual-mode support for virtual prototypes and slice simulations; becoming an important infrastructure for hardware-software collaboration.
Through these collaborations, Horizon embeds its EDA/IP capabilities into various links of the RISC-V industrial chain, injecting a “tools + services” combination advantage into ecosystem construction.
5. Conclusion: Using Product Strategy to Promote the Maturity of the RISC-V Ecosystem
Wu Xiaozhong pointed out that the core bottleneck facing the current development of RISC-V in China is no longer “whether there is an instruction set” but “whether it can be developed, verified, and delivered efficiently,” which is precisely the core value of the EDA toolchain. Horizon Technology is completing a systematic breakthrough that links EDA tool capabilities, IP system capabilities, and RISC-V development through a “fully domestic + deep integration” product path.
This is not only a layout of a single enterprise but also an important example of whether the Chinese RISC-V ecosystem can transition from “chip islands” to “tool collaboration”.
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