1. Introduction to Low-Power Design and UPF Script
In today’s rapidly evolving electronics industry, low-power design has become a crucial topic. With the widespread adoption of electronic devices, from smartphones and tablets to various IoT devices, there are increasing demands for device battery life and energy efficiency. Low-power design not only effectively extends the usage time of battery-powered devices, reduces charging frequency, and enhances user experience, but also lowers the heat dissipation requirements of devices, improving system stability and reliability, which plays a key role in the development of large-scale integrated circuits.
Among the many tools and methods for low-power design, the UPF script (Unified Power Format) stands out as one of the key tools for achieving low-power design. UPF scripts are essentially a set of standards based on the TCL language, primarily used to accurately describe the low-power intentions in chip design. Through UPF scripts, engineers can define the power supply network of the chip in detail, including the division of power domains, the configuration of power switches, the layout of isolation cells, and the configuration of retention register cells, all of which are closely related to power design. This information plays an indispensable role throughout the chip design process, from front-end design and simulation verification to logic synthesis, physical implementation, and finally equivalence verification and sign-off, ensuring the consistency of power intentions at every stage.
2. Principles of UPF Script in Achieving Low-Power Design
The core of UPF script in achieving low-power design lies in its ability to precisely define and control the power architecture within the chip, thereby effectively managing power consumption. This process is mainly achieved through the following key steps:
Defining Voltage Domains
In chip design, different functional modules have varying voltage requirements, and the power consumption needed by the modules also differs under different operating conditions. Through UPF scripts, the chip can be divided into multiple voltage domains. For example, in a mobile processor, high-performance cores may require higher voltage to ensure computation speed, while some low-speed peripheral modules can operate at lower voltages. By using the create_power_domain command to create different voltage domains, the logical units contained in each voltage domain are clearly defined, allowing different modules to operate under the most suitable voltage conditions. This avoids unnecessary high voltage supply, thereby reducing overall power consumption.
Planning the Power Network
The power network is like the “blood vessels” of the chip, responsible for delivering electrical energy to various units. The UPF script defines the structure and connection of the power network through commands such as create_supply_net. In complex chip designs, there may be multiple power networks, such as the main power network, backup power network, and dedicated power networks for specific functional modules. Proper planning of the power network can ensure the stability and efficiency of power supply. By setting the connections and switching relationships between different power networks, flexible power management can also be achieved. When a module enters low-power mode, its main power supply can be cut off, and a backup power supply can provide a small amount of energy to maintain basic status, further reducing power consumption.
Adding Low-Power Cells
To address potential issues during multi-voltage domain design and power switching, UPF scripts introduce a series of low-power cells, such as isolation cells, level shifters, and power switches. Isolation cells are mainly used to ensure the stability of output signals when the power is turned off, preventing signals from floating or erroneously flipping, thus avoiding additional power consumption caused by signal anomalies. Level shifters are responsible for converting signal levels between different voltage domains, ensuring that signals can be transmitted correctly and avoiding signal distortion and increased power consumption due to level mismatches. Power switches are used to control the on/off state of the power supply; when a module is in a non-working state, the power switch can cut off the power supply to that module, effectively reducing static power consumption. In a chip containing multiple functional modules, when a module does not need to work for a period, the power switch can quickly cut off its power, resulting in minimal energy consumption, and the power is only reconnected when needed, significantly reducing the overall power consumption of the chip.
3. Specific Implementation Case: Taking [Project Name] as an Example
(1) Project Background and Requirements
[Project Name] is a smart home control chip aimed at IoT applications, primarily used in smart appliances, security monitoring, and other devices, responsible for key tasks such as data processing, communication, and device control. In IoT application scenarios, devices often need to run for extended periods, and many devices rely on battery power, which imposes very strict requirements on the chip’s power consumption. At the same time, to achieve fast data processing and stable communication functions, the chip must also have a certain level of performance to ensure timely responses to various command and data transmission needs.
In terms of performance, the chip needs to complete a large amount of data computation and processing in a short time, such as real-time analysis of high-definition video streams and complex sensor data fusion calculations, to ensure the efficient operation of the smart home system. However, traditional chip designs often consume a lot of energy when meeting these performance requirements, which contradicts the IoT devices’ demand for long battery life. Therefore, adopting low-power design has become an inevitable choice for this project. By using UPF scripts for low-power design, the power supply and working state of each module in the chip can be precisely controlled, maximizing the reduction of power consumption without affecting performance, extending the battery life of the device, and enhancing the product’s market competitiveness.
(2) Steps to Implement UPF Script
1. Declare Voltage Domains and Virtual Voltage Interfaces: In this project, based on the functional and performance requirements of different modules in the chip, multiple voltage domains were created using the create_power_domain command. For example, for the computation-intensive core processing module, an independent high-voltage domain CORE_DOMAIN was created to ensure its high-speed operation; while for some low-speed peripheral communication modules, a low-voltage domain PERIPHERAL_DOMAIN was created.
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create_power_domain CORE_DOMAIN -elements {core_module1 core_module2} create_power_domain PERIPHERAL_DOMAIN -elements {uart_module spi_module} |
At the same time, the create_supply_port command was used to declare the virtual voltage interfaces required for each voltage domain, such as VDD_CORE and VDD_PERI, which are the power supply ports for the core voltage domain and peripheral voltage domain, respectively, and VSS is the ground port. These virtual voltage interfaces provide a foundation for the subsequent connection and management of the power network.
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create_supply_port VDD_CORE create_supply_port VDD_PERI create_supply_port VSS |
2. Declare Power Networks: Using the create_supply_net command to create power networks for each voltage domain. First, create the main power network and ground network for the top-level voltage domain:
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create_supply_net VDD_CORE_NET create_supply_net VSS_NET |
Then, associate the corresponding power networks with the CORE_DOMAIN voltage domain and ensure the correctness of the network connections:
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create_supply_net VDD_CORE_NET -domain CORE_DOMAIN -reuse create_supply_net VSS_NET -domain CORE_DOMAIN -reuse |
Similar operations are performed for the PERIPHERAL_DOMAIN voltage domain. Next, use the connect_supply_net command to connect the power networks with the previously created virtual voltage interfaces to achieve effective power transmission:
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connect_supply_net VDD_CORE_NET -port {VDD_CORE} connect_supply_net VSS_NET -port {VSS} |
Finally, use the set_domain_supply_net command to specify the main power network and ground network for each voltage domain, clarifying the power supply sources for each voltage domain.
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set_domain_supply_net CORE_DOMAIN -primary_power_net VDD_CORE_NET -primary_ground_net VSS_NET set_domain_supply_net PERIPHERAL_DOMAIN -primary_power_net VDD_PERI_NET -primary_ground_net VSS_NET |
3. Add Power Switch: To further reduce the static power consumption of the chip, add a Power Switch in the voltage domain of some infrequently used modules. For example, in the PERIPHERAL_DOMAIN, the spi_module can have its power supply cut off when it is in a non-working state through the Power Switch. First, use the create_power_switch command to create the Power Switch instance:
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create_power_switch spi_switch -domain PERIPHERAL_DOMAIN -input_supply_port {in VDD_PERI} -output_supply_port {out VDD_PERI_MODULE} -control_port {spi_ctrl_signal uart_module/spi_ctrl} -on_state {state_on in {!spi_ctrl_signal}} -off_state {OFF {spi_ctrl_signal}} |
Here, the input and output power ports of the Power Switch are specified, along with the control signal spi_ctrl_signal. When spi_ctrl_signal is high, the Power Switch is in the off state, cutting off the power to the spi_module; when spi_ctrl_signal is low, the Power Switch is on, supplying power to the spi_module.
4. Establish Power State Table (PST): The power state table (PST) is used to define the power state combinations of different voltage domains under various working states, providing important basis for power consumption analysis and simulation. In this project, the add_port_state command is first used to define different states for each power port, such as:
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add_port_state VDD_CORE -state {ACTIVE 1.2V} add_port_state VDD_CORE -state {SLEEP 0.8V} add_port_state VDD_PERI -state {ACTIVE 1.0V} add_port_state VDD_PERI -state {OFF 0V} |
Here, the voltage of the core voltage domain VDD_CORE is defined as 1.2V in the active state (ACTIVE) and 0.8V in sleep state (SLEEP); the peripheral voltage domain VDD_PERI has a voltage of 1.0V in active state and 0V in off state (OFF). Next, the create_pst command is used to create the power state table, and the add_pst_state command is used to add different power state combinations to the table. For example, define a state combination where the core module is in active state and the peripheral module is in off state:
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create_pst SYSTEM_PST -supplies {VDD_CORE VDD_PERI} add_pst_state SYSTEM_PST -name {CORE_ACTIVE_PERI_OFF} -state {ACTIVE OFF} |
5. Insert Isolation Cell: Between different voltage domains and the signal output terminals in the power-off area, it is necessary to insert an Isolation Cell to prevent incorrect transmission or floating phenomena of signals during power state changes. For example, using the signal connection between CORE_DOMAIN and PERIPHERAL_DOMAIN, the set_isolation command is used to insert the Isolation Cell:
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set_isolation -from {CORE_DOMAIN} -to {PERIPHERAL_DOMAIN} -cell_type ISOLATION_CELL_TYPE -control_signal {iso_ctrl_signal} |
Here, the insertion direction of the isolation cell is specified from CORE_DOMAIN to PERIPHERAL_DOMAIN, the type of isolation cell used is ISOLATION_CELL_TYPE, and the control signal is iso_ctrl_signal. When iso_ctrl_signal is valid, the isolation cell operates, ensuring stable signal transmission.
6. Replace with Retention Register Cell: For some registers that need to retain data even after power is turned off, use the Retention Register Cell for replacement. In the CORE_DOMAIN, some registers are used to store critical configuration information and intermediate computation results, and these registers need to maintain their data unchanged when power is turned off and restored. The set_retention command is used to implement this replacement:
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set_retention -elements {register1 register2} -cell_type RETENTION_REGISTER_CELL_TYPE -save_control {save_signal} -restore_control {restore_signal} |
Here, the registers to be replaced are specified as register1 and register2, the type of Retention Register Cell used is RETENTION_REGISTER_CELL_TYPE, the save control signal is save_signal, and the restore control signal is restore_signal. Before power is turned off, when save_signal is valid, the register data is saved; when power is restored, when restore_signal is valid, the register data is restored.
7. Insert Level Shifters: When signals are transmitted between different voltage domains, due to different voltage levels, it is necessary to insert Level Shifters for level conversion to ensure correct signal transmission. In the signal transmission path between CORE_DOMAIN (1.2V) and PERIPHERAL_DOMAIN (1.0V), the set_level_shifter command is used to insert Level Shifters:
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set_level_shifter -from {CORE_DOMAIN} -to {PERIPHERAL_DOMAIN} -cell_type LEVEL_SHIFTER_CELL_TYPE |
Here, the direction of level conversion is specified from CORE_DOMAIN to PERIPHERAL_DOMAIN, and the type of level shifter used is LEVEL_SHIFTER_CELL_TYPE, ensuring that signals can be accurately transmitted between different voltage domains.
(3) Challenges and Solutions During Implementation
During the actual writing and application of UPF scripts, many issues were encountered. First, syntax errors occurred due to the strict syntax rules of the TCL language on which UPF scripts are based, often resulting in command parameter errors, mismatched parentheses, etc. For example, when using the create_power_domain command, mistakenly writing the -elements parameter as -element caused the tool to fail to correctly identify the modules contained in the voltage domain, leading to errors in subsequent synthesis and implementation processes. The solution to such problems is to carefully consult the syntax manual for UPF scripts, utilize the syntax checking function of the script editor, and check the written scripts line by line to promptly identify and correct syntax errors.
Secondly, power conflicts are also a common issue. In complex chip designs, there may be potential conflicts between different power networks and voltage domains, such as short circuits in power networks and signal cross-interference between different voltage domains. In this project, there was a case where the power networks of two different voltage domains short-circuited during the physical implementation phase, causing the chip to fail to operate normally. After careful investigation, it was found that there was an error in defining the connection relationships of some networks when declaring the power networks. By rechecking and correcting the connection commands of the power networks, ensuring the independence and correctness of each power network, the power conflict issue was successfully resolved. Additionally, during the design process, professional power analysis tools were used to simulate and verify the power networks, allowing for the early detection and resolution of potential power conflict risks.
Furthermore, inserting various low-power cells (such as Power Switch, Isolation Cell, etc.) may impact the chip’s timing, leading to timing violations. To address this issue, after inserting low-power cells, timing analysis tools were used to conduct a comprehensive analysis of the chip’s timing. For paths with timing violations, methods such as adjusting the layout of low-power cells and optimizing signal routing were employed to improve timing performance, ensuring that the chip meets timing requirements while achieving low power consumption.
4. Evaluation of Case Effectiveness
(1) Power Consumption Reduction Data Comparison
After completing the writing and implementation of the UPF script, detailed testing and analysis of the power consumption of the [Project Name] chip were conducted. Using professional power testing equipment, the power consumption data of the chip in different operating modes before and after applying the UPF script for low-power design was measured.
In normal operating mode, when the UPF script was not used, the total power consumption of the chip was 150mW. After applying the UPF script for low-power design, the total power consumption of the chip was reduced to 100mW, a reduction of approximately 33.3%. This is mainly due to the fine management of different voltage domains and the effective application of Power Switch. When some non-critical modules enter low-power states, the Power Switch can promptly cut off the power supply, avoiding unnecessary energy consumption.
In sleep mode, the power consumption of the chip before optimization was 50mW, and after optimization with the UPF script, the power consumption in sleep mode was reduced to 10mW, a reduction of up to 80%. This significant reduction is mainly because, in sleep mode, the power supply to most modules is completely cut off, leaving only a few necessary wake-up circuits and low-power units to maintain basic status, greatly reducing static power consumption. Through these specific data comparisons, it is evident that the UPF script has achieved remarkable results in reducing chip power consumption, effectively enhancing the chip’s energy efficiency and providing strong support for the long battery life of IoT devices.
(2) Performance Impact Analysis
While focusing on power consumption reduction, an in-depth analysis was also conducted on whether the application of UPF scripts had any impact on chip performance. In terms of running speed, due to reasonable voltage domain division and power management strategies during the design process, it was ensured that high-performance modules could obtain sufficient voltage and stable power supply when needed, thus the chip’s running speed during critical tasks, such as data processing and communication protocol parsing, was not significantly affected. In some benchmark tests, the time taken by the chip to complete the same tasks before and after using the UPF script remained basically consistent, indicating that the low-power design of the UPF script did not come at the expense of the chip’s running speed.
In terms of stability, although various low-power cells (such as isolation cells, level shifters, etc.) were inserted, strict timing analysis and optimization ensured the correct transmission of signals between different voltage domains and the stability during power state switching. After long-term reliability testing, the chip was able to operate stably in various complex environments without experiencing system crashes or data errors due to low-power design. This indicates that the UPF script effectively ensures the stability and reliability of the chip while achieving low power consumption, laying a solid foundation for its widespread use in practical applications.
