According to a report from Electronic Enthusiasts (by Zhou Kaiyang), general-purpose computing chips are rarely optimized for AI computations, which is why in many AI applications, we still need traditional AI chips, such as GPUs or ASICs, which are larger in area and power consumption. Due to these limitations, these AI chips are difficult to deploy at the edge.So, can edge AI be handled by MCUs? Traditional MCU designs still find it challenging even for light AI computations. Therefore, many MCU manufacturers are starting to develop higher-performance MCUs, adopting designs specifically optimized for AI to promote the proliferation of edge AI.
Ultra-High-Performance Cores
Considering that many MCUs are still using low-power cores like Cortex-M4, M3, or even M0, the computational power required for complex embedded AI algorithms makes these old cores insufficient for such applications. Since there is a performance disadvantage, the solution is to directly break through in terms of performance. In recent years, many MCU products based on ultra-high-performance cores have emerged, such as the GD32H7 based on the Cortex-M7 core.The Cortex-M7 core, as the successor to the Cortex-M4, is developed based on the Armv7E-M architecture. From the perspective of core key features, the Cortex-M7 is one of only two cores with more than six stages of pipeline design among all Cortex-M processors, the other being the seven-stage pipeline Cortex-M85 core, which has not yet officially been released.GigaDevice has achieved a main frequency of 600MHz on the GD32H7, even surpassing many foreign manufacturers’ Cortex-M7 MCUs. Such a high frequency is sufficient to meet the AI computational requirements at the edge, eliminating the need to integrate additional NPUs. Moreover, to accommodate the resource requirements of AI algorithms, the GD32H7 is equipped with on-chip Flash ranging from 1024KB to 3840KB and 1024KB of SRAM.In addition to Arm cores, RISC-V manufacturers like StarFive have also launched ultra-high-performance RISC-V MCUs such as the HPM6700/6400 series. Among them, the HPM64G0 can achieve a single-core main frequency of 1GHz, supports double-precision floating-point operations, and also features a powerful FPU and DSP extension, sufficient to meet the computational needs of many TensorFlow Lite models.
Multi-Core MCUs
Another approach to solving performance issues is to adopt multi-core MCU designs. Manufacturers like STMicroelectronics have already begun to layout dual-core MCU products several years ago. For example, the STM32H7 series includes products that integrate both Cortex-M7 and Cortex-M4 cores, such as the STM32H747/757.These two independently operating cores can be assigned different tasks, with the Cortex-M7 handling high-performance tasks and the Cortex-M4 handling real-time tasks. Additionally, with the STM32Cube.AI tool provided by ST, existing AI algorithms and pre-trained models can be converted into runnable code. If larger models over 1Mbyte need to be run, more Flash memory can be allocated to the Cortex-M7.In addition to the dual Cortex-M core design, some manufacturers are also exploring collaboration between different architecture cores. For instance, ADI’s MAX78000 chip integrates an Arm Cortex-M4 core with a RISC-V core; in addition, this MCU also includes a neural network accelerator.Moreover, in the MAX78000, ADI has clearly defined the roles of these three components, with the Cortex-M4 responsible for MCU control and processing, while the RISC-V core acts as a coprocessor responsible for data handling, and the neural network accelerator enhances CNN computation efficiency. This architecture offers advantages in terms of power consumption and parallelism compared to traditional MCU + DSP solutions.
Final Thoughts
Although many players in the current MCU market are already focusing on edge AI, manufacturers also need to build a robust software ecosystem, providing complete example codes or usable models to achieve true out-of-the-box usability. At the same time, there is still room for further performance improvements in MCUs. For instance, many MCUs participating in edge AI computations can only use pre-trained models. When can MCUs complete both lightweight training and inference tasks at the edge? The application space will be even broader.
Disclaimer: This article is originally written by Electronic Enthusiasts, please indicate the source above when reprinting. For group discussions, please add WeChat elecfans999, for submissions or interview requests, please send an email to [email protected].
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