On July 17, 2025, the 2025 RISC-V China Summit will officially be held in Zhangjiang, Shanghai, China. Professor Krste Asanović, one of the inventors of RISC-V technology and co-founder and chief architect of SiFive, presented the theme “State of the Union,” introducing the evolution direction of RISC-V technology: the RVA23 standard is about to be implemented, and it will iterate to RVA30 around 2030, with the development of long instruction sets exceeding 32 bits starting, and the construction of vertical industry ecosystems becoming the core task of the new phase.
Professor Krste Asanović began by reviewing the history of RISC-V technology development, which has been divided into three stages over the past 15 years: the first five years broke through academic skepticism and completed architecture definition, the middle five years built the foundational software ecosystem, and the last five years saw an explosion in vertical industries. Currently, the annual shipment of RISC-V chips has reached tens of billions, especially showing exponential growth in the AI accelerator field. “Open standards are becoming the mainstream ISA (Instruction Set Architecture), and their simplicity and flexibility far exceed any closed architecture.”
As a mainstream open-source ISA, the characteristics of RISC-V in one vertical industry application can also be utilized in another vertical industry, and the open standard allows for better reusability. At the same time, achieving greater success in any vertical field requires not only a single component but also the efforts of various components across different fields to further improve the RISC-V ecosystem. Therefore, Professor Krste Asanović pointed out, “We need to continuously develop supporting components for RISC-V, which will have some specific necessary features that must be compatible.”
For example, RVA23 was approved in October 2024. This standard addresses the fragmentation issue within the RISC-V ecosystem through unified ISA extensions, providing developers with consistency across hardware platforms and enhancing high-performance computing capabilities such as vector computation and floating-point operations.
Professor Krste Asanović expects that RVA23 will be a very standardized document or configuration content in the ISA configuration process in the coming years. “We have also collaborated with some ecosystem partners, including Linux and Android, to ensure that RISC-V possesses various features and can be more competitive across different processors. We support different features to ensure that the software ecosystem can rely on such features. Hardware solutions for RVA23 are expected to be launched soon.”
Professor Krste Asanović also previewed that the next version of RVA23, tentatively named RVA30, may not be released until around 2030, and many members of the RISC-V Alliance have already begun to focus on this aspect. Throughout the roadmap, smaller versions such as RVA23.1 and RVA23.2 will also be released in due course, although they will not include major features but will add some minor options. However, some of these optional features may become essential major features in RVA30. Therefore, in terms of software development support, efforts must be made in parallel to accelerate the arrival of RVA30.
It is reported that during this process, SiFive may use a binary approach to utilize many related software, and hardware vendors will also use the same binary code. Another aspect is the RVM microcontroller specification, which includes a subdivision for automotive microcontrollers and related standards. SiFive will also utilize open-source standards to enhance this, empowering the entire automotive vertical. “Now we are not only focusing on the application of the entire processor, but we also hope to apply it to different verticals. Through this approach, we can better support the development of RISC-V microcontrollers with the entire software toolkit,” said Krste Asanović.
SiFive is also developing new RISC-V related security extension features, such as SPMP (Second Level Memory Protection). Krste Asanović pointed out that SPMP will provide us with a second level of memory protection, allowing us to map different microcontrollers to the entire system, providing strong security features.
Meanwhile, long instructions (greater than 32 bits) are also a significant direction for the future. RISC-V has included variable-length instructions from the beginning to save code space and compress instructions (16 bits), which helps reduce code size. The design of RISC-V aims for long-term success and will not disappear due to changes in ownership business models or bankruptcy. The fixed 32-bit instruction format will become an obstacle to long-term evolution, as the fixed-width 32-bit ISA encoding space is already constrained. Longer instructions also help reduce code size, improve performance, and support an increasing variety of data types.
For AI, RISC-V supports a general computing model that allows for a balance of scalar, vector, and matrix capabilities. At the same time, developers can achieve this balance with better and smaller systems, and can implement it in different ways to create a more stable runtime environment, ensuring high-level operation of AI tools and performance.
RISC-V has different matrix extension methods that involve various systems, and there are four different methods for related matrix extensions: first, there will be more support from matrix and vector engines; second, there will be ordinary vector function units, then to their carriers, and finally to their memory.
“RISC-V is a very important foundational component that is now in place and running well, and is entering various vertical fields. Each vertical needs to focus on building ecosystems and filling gaps in instruction set architecture or software support while maintaining the coherence of the overall instruction set architecture design. RISC-V provides us with a simple, flexible, and efficient standard, allowing us to better deploy and utilize AI globally.”
Editor: Chip Intelligence – Lang Ke Jian
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