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2025.05
In May 2010, Andrew Waterman, a student at the University of California, Berkeley, sent an email to his professors. After experimenting with various teaching methods for a three-month project, he concluded:
They should revive the dying microprocessor architecture DEC Alpha.
“I don’t see what new things we can create,” Waterman said. “This has nothing to do with ISA design — it’s an intellectually stimulating, creative, and technical task in itself. But developing compilers, operating systems, and porting a bunch of software? I think that’s a multi-billion dollar project, far beyond the understanding of a few scholars.”
However, for Professor Krste Asanović, principles outweighed preferences: none of the existing ISAs met their needs. “In my view, there was no choice,” Asanović said. “Alpha was fast, but there were many architectural issues. I didn’t want those burdens.”
Asanović speculated that the team had lingered too long between daunting commercial ISAs and those that were less constrained but flawed or declining. Moore’s Law was slowing, and Dennard scaling was about to end, necessitating specialization, customization, and parallelism. For this, they needed a fresh start.
Asanović, Waterman, and graduate student Yunsup Lee discussed this in several emails. Ultimately, on May 18, 2010, Waterman compromised and accepted the risks of the new RISC.
By the way, let me talk about the pun on RISC/risk. The title authors always benefit from it, but many are unaware that they are deliberately borrowing from Dave Patterson, the father of RISC. “We thought that government agencies known for funding high-risk, high-reward projects might be more favorable to us,” he told me.
Patterson’s bet paid off when he created the first RISC architecture in 1980. In 2005, he founded the Par Lab at UC Berkeley, and five years later, RISC-V became the fifth major RISC ISA launched from the university under his guidance.
In the 15 years since that Tuesday in 2010, RISC-V has not only become the third largest ISA on Earth but has also reached the Moon. High risk? Perhaps. High reward? Absolutely.
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Finding Niche Markets
There are two common assumptions about RISC-V: that the team initially set out to build an open-source architecture and that they had to work hard to break free from the constraints of academia.
“We stipulated that it had to be easy for small university teams to build, must be efficient, and easy to scale,” Asanović said. “The open requirement stemmed from our desire to share our results with friends through the Berkeley Software Distribution License. We wanted to push the academic computer architecture community back to real RTL hardware design, away from C models that might or might not work in the real world.”
In the following years, RISC-V was purely a tool for parallel computing and processor design courses and research. But getting attention from academia outside Berkeley proved more challenging than expected. “Academia was very skeptical,” Asanović said. “To them, it was just another RISC ISA to learn. The fact that it was an open standard didn’t interest them — they wanted to teach what was being used in the industry. So they continued to focus on x86 development.”
Everyone should know the “RISC-V Four Giants” — Asanović, Waterman, Lee, Patterson. But one name you might not be familiar with is independent computer architect and Berkeley alumnus John Hauser. Asanović calls him “the fifth Beatle.”
“Hauser played a significant role in shaping the ISA,” Asanović said. “The ecosystem owes him for the hypervisor in 2020 and the advanced interrupt architecture (AIA) in 2023. But we might also owe him an apology — because when he told us RISC-V would be a hit, we were not ready to believe him.”
The first version of the RISC-V instruction manual was released in May 2011. However, it wasn’t until the team modified the ISA design in a few classes at UC Berkeley that they realized they had users outside of Par Lab. Suddenly, people on the other side of the Earth began questioning why they were changing certain things.
“We knew this was a niche market,” Asanović said. “We just didn’t expect we would also fill that market for others. Many focused on the technical side. Technically, is it better than other ISAs? In hindsight, RISC-V’s success did not stem from its technical advantages but from its openness. The real innovation was in the business model.”
“We didn’t apply any pressure,” Waterman said. “If there was any influence, it was a gentle push when the project was completed in 2014. Since it was done, we didn’t dwell on it anymore. That’s when things really started to take off.”
Industry Pull
The IEEE Hot Chips 26 symposium held in Cupertino from August 10 to 12, 2014, was eye-opening. “We were very surprised by the attraction from the industry,” Asanović said. “When we attended the conference, we thought we would need to push this hard. Clearly, we greatly underestimated the desire for an open ISA.” By January 2015, when the team held the first RISC-V workshop in Monterey, the balance had truly shifted. “We expected very few participants from academia,” he said, “but in fact, 40 different companies attended the meeting.”
But openness was not the only attraction. Another major complaint the team heard was the lack of flexibility in commercial ISAs. The main benefit of RISC-V to the industry was flexibility, not cost. However, RISC-V’s openness not only reduced costs but also eliminated cumbersome procedures. “Startups told us that signing contracts could take up to two years, which caught them off guard,” Asanović said. “With RISC-V, they could use it that afternoon. We didn’t need to convince anyone that this was a good thing.”
That year, Asanović and Patterson published a groundbreaking positioning paper titled “Instruction Sets Should Be Free: The Case For RISC-V,” further fueling the momentum. In the paper, they doubled down on openness, comparing it to open standards like TCP/IP, Ethernet, C language, and Linux.
This paper had a profound impact on the industry. Mike Aaronson of Rumble Technologies read it and migrated an FPGA-based camera project from MIPS to RISC-V within three weeks. This became the first commercial product using RISC-V.
At the fourth RISC-V workshop held in July 2016, NVIDIA announced plans to replace its proprietary Falcon core (used for power management and security tasks within GPUs) with RISC-V to meet 64-bit requirements. This move ultimately led to NVIDIA delivering one billion cores in 2024 alone. At the time, this may not have garnered much attention. But it was significant: a top semiconductor company chose RISC-V to perform critical internal functions.
Months later, the fifth RISC-V workshop was held at a Google facility in Silicon Valley. “The participation from the industry far exceeded previous years, with 107 companies and 30 universities involved,” said Larry Lapides, executive director of RISC-V tools business development at UK-based Imperas (now acquired by Synopsys). “The talks and interactions I attended there convinced me that RISC-V was absolutely mature and ready for industry adoption.”
Today, Larry and CEO Simon Davidmann recognize future opportunities, positioning Imperas as a leading force in the RISC-V journey — dedicated to shaping its commercial future and supporting ecosystem development. Imperas’ commercial software tools, including simulators and verification suites, have been widely adopted across the ecosystem, accelerating its maturity and establishing best practices for design verification.
The Final Embrace of Education
As RISC-V’s momentum reached a critical point, academia finally acknowledged industry demand and accepted RISC-V as a teaching architecture.
“We converted all course materials to RISC-V from top to bottom,” Asanović said. “And, as is often the case in academia, institutions would ‘borrow’ from the experiences of top universities. Making slides was easy, but building labs required a lot of energy, effort, and engineering work. Ultimately, when our full suite of resources began appearing in other university programs, we knew we had made an impact.”
RISC-V gradually penetrated academia. Numerous institutions worldwide, including MIT, ETH Zurich, and the University of Bologna, adopted RISC-V in their teaching and research programs, developing course materials and lab exercises using its open-source features.
As early as 2013, ETH Zurich and the University of Bologna launched a new open-source project called PULP (Parallel Ultra-Low Power) based on OpenRISC. The project was led by Luca Benini, head of the Digital Circuits and Systems Department at ETH Zurich, along with Frank K. Gürkaynak, a senior scientist at ETH Zurich and director of the Microelectronics Design Center, and project leader Professor Davide Rossi.
Gürkaynak revealed, “The initial idea of PULP was not to design our own processor core. But after several discussions with proprietary core vendors, we realized the need to open access to these cores for experimentation and to share our improvements with other partners.”
The PULP team has been working hard to achieve the desired performance using OpenRISC. Subsequently, Rossi attended the first RISC-V workshop and training camp held in Monterey in 2015. “I realized that migrating from OpenRISC to RISC-V made a lot of sense because it had a larger community,” he said. “By the end of 2015, we had migrated all cores to RISC-V.”
“For those of us interested in researching new architectures and possibilities, the ability to freely develop, experiment, and share processor implementations has opened many doors for us,” Gürkaynak explained. “Based on our widely used and licensed implementations, we were able to collaborate more quickly in academia and industry. RISC-V benefits us, and we benefit RISC-V.”
Leaving the Lab
As RISC-V went global, it was time to separate it from Par Lab. “Everyone knows that graduate student projects die once the thesis is submitted,” Waterman said. “We needed something more stable to carry this standard.”
Thus, the RISC-V Foundation was established in 2015 to promote openness, neutrality, and prevent fragmentation while establishing the ISA as a legal entity. Of course, it was also to ensure its sustainability as academia transitioned to new fields. One of the key figures in this transformation was Rick O’Connor, who played a central role in guiding the early governance model and helped lay the groundwork for industry-friendly architecture as the foundation’s founding executive director. Rick has been a strong advocate for moving RISC-V from the lab to an independent foundation, and his leadership has played a crucial role in bridging the gap between academic origins and commercial applications, ensuring the foundation could expand with the growing interest.
“Rick’s idea was that companies joining in the first year would become founding members; they would help us draft the membership charter and plan future operations,” Asanović explained. “I expected six companies to register, but ultimately there were 42 founding members — including Google, NVIDIA, IBM, Western Digital, Qualcomm, and Microchip. Suddenly, we had 42 legal departments — some even had entire floors of legal teams — carefully reviewing the details.”
“The foundation’s mission is to unite everyone, but that’s not easy,” said Jeffrey ‘Jefro’ Osier-Mixon, former board secretary of the foundation and current distinguished community architect in the CTO office at Red Hat. “We did our best to be as open and transparent as possible.”
He continued that there had to be a membership agreement, purely by design. “The agreement also contained some deep clauses to protect patents between members. Explaining to the community why this agreement was needed (and why it needed to be signed) was not always easy, but it was crucial for ensuring trust and collaboration among different stakeholders.”
Meanwhile, Asanović, Waterman, and Lee began commercializing RISC-V through SiFive. They envisioned this new company providing custom chips to meet specific application needs. Each project would be unique, capital-intensive, and with limited opportunities for reuse — not only leveraging RISC-V but also all other innovations they conceived in Par Lab.
“Before they gave us Series A funding, we didn’t even have a brochure, let alone a business model,” Asanović said. “At the time, it felt like, ‘Look, you all seem smart, don’t let us down.’” But the team did not have the privilege of being an invisible startup. Everyone was watching what the RISC-V team would do next. Soon, dozens of large companies were asking them for reusable core IP modules.
“We thought carefully and felt that if we did it their way, it would help RISC-V gain traction,” Asanović said. “This might also help us land in these companies and expand our business, seeing what other projects we could participate in.” After manufacturing some custom cores in the embedded field, SiFive turned to the IP business.
A Growing Ecosystem
From 2015 to 2019, commercial demand began shifting towards production-ready IP. While the open-source nature of the ISA fostered innovation, especially in academia, the burden of functional verification — which often consumes 75% of development time and cost — remained a significant barrier to entry, especially in advanced process nodes: designing on a 3nm process requires design teams of thousands of engineers to spend tens of thousands of hours, with hundreds of millions of dollars spent just on the functional verification step.
Companies were no longer reinventing the wheel but began opting to obtain verified core licenses from emerging commercial IP vendors. For many of these vendors, RISC-V drove a significant transformation in their business models. Zdenek Prikryl, CTO of Codasip, stated, “We evolved from a pure EDA (Electronic Design Automation) company to one that combines IP and EDA expertise. This shift has positioned us at the forefront of RISC-V processor design and customization — providing true heterogeneous and specialized computing capabilities, and allowing us to explore and implement community innovations like CHERI (Capability Hardware Enhanced RISC Instructions) security extensions.”
After nearly a decade of independently developing embedded IP, Andes Technology officially embraced RISC-V at the 2016 RISC-V workshop. “RISC-V perfectly aligns with our strengths in scalability, customization, and real-time computing,” said Frankwell Lin, chairman and co-founder of Andes Technology. “RISC-V not only impressed us but also gave us the opportunity to be part of a vibrant global community where we share knowledge, co-develop standards, and accelerate industry applications.”
At the same RISC-V workshop, storage giant and founding member Western Digital (WD) announced it was migrating its processor cores to RISC-V. In 2019, WD CTO Martin Fink announced a goal of over one billion RISC-V cores shipped annually — equivalent to IBM’s historic $1 billion investment in Linux in 2000. This commitment marked the most significant public support from an established mass production manufacturer to date, and Western Digital ultimately delivered on that promise.
Speaking of Linux, around this time, RISC-V and the Linux Foundation announced a joint collaboration agreement aimed at accelerating development and application. Calista Redmond succeeded Rick O’Connor as CEO, overseeing the foundation’s transition to the RISC-V International Association (RVI) in 2020. The association is now headquartered in Switzerland, aiming for unrestricted access and geopolitical neutrality. As part of this transition, RISC-V International began leveraging the Linux Foundation as a service provider for infrastructure, governance, and community support.
Redmond’s tenure ushered in a new era of global strategic growth. She spearheaded a series of initiatives to expand RISC-V’s influence into new regions and industries while positioning the architecture as a pillar of global digital sovereignty. Despite the COVID-19 pandemic disrupting the global economy and triggering chip shortages, industry participation continued to grow rapidly, and the commercial ecosystem was thriving.
Rick O’Connor served as president and CEO of the OpenHW Group until his retirement in 2023. The OpenHW Group is a newly established non-profit global organization dedicated to promoting developer collaboration and advancing RISC-V hardware applications in commercial and academic fields. The OpenHW Group currently has its own series of RISC-V cores aimed at providing industrial-grade open-source hardware, allowing the community to integrate their breakthrough IP and unique innovations.
OpenHW CEO Flo Wohlrab noted, “Before RISC-V, CPU IP was constrained by restrictive NDAs, high NRE costs, and patent fee models, making open collaboration at the chip level nearly unimaginable. Today, thanks to RISC-V and OpenHW, we see a global ecosystem where companies not only adopt open cores but actively build products and create entirely new markets around them.”
RISC-V Without Borders
Especially in the past five years, RISC-V has established a foothold on the world stage. “RISC-V is now a truly global entity,” Osier-Mixon said. “Countries are actively engaging with RISC-V at the government level, pursuing digital sovereignty. Who would have thought 15 years ago that countries like Brazil and India would make it the core of their national computing architecture? You think of it as a national bird or flag — but actually, it’s a computing architecture? That’s incredible.”
But these developments are not coincidental. Redmond has persistently guided RVI to become a neutral platform for open computing — engaging in dialogue with governments and policymakers and aligning its architecture with strategic technology independence plans.
Brazil has strengthened its role in the RISC-V ecosystem and became a senior member of RISC-V International in February 2024. In July 2025, São Paulo will host the second RISC-V Brazil event, continuing to strategically promote open standard innovation in Latin America.
India’s involvement with RISC-V began in 2014 with the Shakti project, initiated by the Indian Institute of Technology Madras and supported by the Ministry of Electronics and Information Technology (MeitY). This academic effort laid the groundwork for India’s broader RISC-V ambitions. In 2022, MeitY launched the “Digital India RISC-V” (DIR-V) initiative to promote the development of indigenous RISC-V processors to meet strategic and commercial application needs. This has become a key component of India’s “Atmanirbhar Bharat Abhiyaan” (Self-Reliant India Movement).
“Even long ago, countries like India recognized that RISC-V is very beneficial for national security. They don’t have to rely on foreign vendors for critical computing infrastructure,” Asanović said.
In the past 15 years, awareness of state-sponsored cyberattacks has significantly increased. Concerns about IT security have also intensified. Therefore, countries are prioritizing their national security interests and recognizing that achieving this goal requires building trustworthy and autonomous hardware implementations.
“If it’s proprietary and owned by different national actors, then trust doesn’t exist,” Asanović said. “You need an open standard — that way you can reuse software and run it on your own, trusted hardware.”
Especially in China, it has viewed RISC-V as a pathway to architectural autonomy. In 2019, Alibaba’s chip subsidiary T-Head announced its first RISC-V project — the Xuantie 910, a commercial multi-core 64-bit processor with vector extension capabilities, bringing RISC-V into the mainstream of Chinese technology and laying a solid foundation for the future development of Chinese chip manufacturers. A year later, the Institute of Software, Chinese Academy of Sciences (ISCAS) released China’s first RISC-V-based openEuler Linux distribution.
ISCAS has also made significant progress in virtualization, contributing to projects like Kata Containers and Cloud Hypervisor. Their latest milestone — a new RISC-V image based on LLVM and supporting vectors — has been successfully tested on the K1 development board, marking an important step forward for openEuler, China, and the broader RISC-V community.
Vertical Alignment
Last year, the approval of the application-level RVA23 specification marked another milestone for the architecture. With its built-in key components — vectors, hypervisors, and cryptography, RVA23 has played a crucial role in extending RISC-V into areas such as AI, automotive platforms, and rich operating system (OS) environments like Android.
Andrea Gallo, the new CEO of RISC-V International, stated, “The profiles are the foundation for the portability of applications and system software across RISC-V implementations. Only by having a standard profile for software vendors to choose from, and multiple vendors able to collaborate within it, can we achieve a large software ecosystem.”
As the foundational gaps narrow, the focus is shifting towards achieving complete ecosystems in specific vertical markets, each with different needs: software frameworks, toolchains, real-time capabilities, security standards, and core implementations optimized for performance, power, and area.
“RVA23 is an important milestone for me because it means we no longer question ‘Can RISC-V do it?’ — it can,” Asanović said. “The ISA has matured, the toolchain is stable, and the core functionality is strong.”
However, he noted that the profile is general — it is not tied to any specific vertical market. As higher-performance cores emerge and familiarity with RISC-V foundational components increases, we will see new ecosystems emerge around each vertical.
However, he cautioned that we should not rush to create profiles for every vertical industry. “Each vertical industry needs a complete solution. For example, we will precisely identify everything needed to build a successful automotive MCU profile and gather all necessary components. The worst-case scenario is that we provide 90% of the solution for 100 markets. The better scenario is to provide a 100% solution for 10 markets.”
“This is precisely why the 15th anniversary of RISC-V is such an important turning point,” Gallo said. “In the coming years, the RISC-V ecosystem will enter a new phase, with high-performance cores and broader industry confidence driving targeted ecosystem development in aerospace, automotive, data centers, embedded systems, high-performance computing (HPC), and security.”
AI Takes Center Stage
RISC-V can also accelerate the design of workload-driven processors. Chip designers can customize designs based on specific application and domain needs, optimizing for various compute-intensive AI workloads ranging from generative AI to autonomous navigation.
Gallo stated, “RISC-V can directly integrate instructions tailored for machine learning (ML) and other data-intensive tasks into the processor. This helps develop dedicated in-core and near-core hardware accelerators for common operations in these workloads, such as matrix multiplication or tensor operations.”
Gallo noted that AI will be the glue that binds everything together. “It runs through every industry. That’s why we are so focused on AI, from software to the foundational instruction set (ISA). Across verticals, from automotive to supercomputers, we want developers to have the tools and intelligence they need.”
The goal of RISC-V is simple: to become the industry-standard ISA for all computing devices across all verticals. When I ask people what they think is hindering the development of the RISC-V ecosystem, the answer is always the same — software.
Davide Rossi, an associate professor at the University of Bologna, stated, “The biggest challenge RISC-V will face in the next 15 years will be creating a mature software ecosystem — especially for HPC.”
“It’s a bit like the chicken and egg problem,” Asanović said. “Building a core optimized for a specific vertical market is meaningless without software to run on it, but no one will write software for a core that doesn’t exist. So the entire industry needs to evolve together.”
“The last domino to fall is likely to be application servers and mobile devices, as the software install base in these two areas is simply enormous,” Waterman said. “First, we will see RISC-V used for more specialized tasks in these devices — such as network packet processing, AI-optimized traffic routing, power management, and security.”
Waterman predicted in 2010 that software would be the biggest barrier to RISC-V, and that prediction still holds true today. But unlike before, this is no longer just a field for a few scholars. Today, ambitious projects like the RISC-V Software Ecosystem (RISE) project are laying the groundwork for commercial success by establishing a robust and scalable software ecosystem with production-grade toolchains, runtime environments, virtualization, and OS-level integration for application processors.
RISE was founded in May 2023 by companies including Qualcomm, Google, Intel, NXP, NVIDIA, Red Hat, and Samsung, providing over $1 million in funding through member contributions and contracts awarded externally, and has been dedicated to advancing upstream open-source software projects.
Amber Huffman, chair of the RISE management committee, stated, “Miracles happen when the community comes together to solve problems. We established RISE because we recognized the need for collaboration to provide high-performance, commercially viable software for RISC-V.”
Like Asanović, Huffman believes this is a “chicken and egg” problem. “For success, a new instruction set architecture and its features must be supported by strong underlying software,” Huffman explained. “But this software is often built only after the platform is adopted. So the entire industry needs to evolve together.”
To support the developer ecosystem, RISE has released RISC-V optimization guidelines and recently launched a RISC-V Developer Rewards Program to reward developers who port, test, and release open-source projects on RISC-V. This is just two of many contributions from the RISE community that are driving the development of RISC-V open-source software.
With the comprehensive establishment of the software stack, the era of RISC-V will truly arrive. Zdenek Prikryl of Codasip stated, “In the next 15 years, RISC-V will truly cross the chasm and be widely adopted in the mainstream. I envision future desktop and laptop computers based on RISC-V will stand alongside other architectures and mature, keeping pace with existing ecosystems. While we have seen progress toward this vision, I believe the most exciting developments are still ahead.”
Flo Wohlrab of OpenHW stated, “Fifteen years from now, the OpenHW Foundation will be the go-to place for high-quality open-source cores. Chip manufacturers will use these cores just as Linux is widely used in the industry today — a large and vibrant ecosystem will bring more and faster innovations.”
V for Vector
The “V” in RISC-V also stands for vector, which is no secret — it reflects Asanović’s long-held vision of vector processing as a core function of the ISA. “It’s great to see everyone excited about vectors again,” he said. “The chip I designed in the early 1990s was a vector machine for running neural networks.”
This intent was later realized in the RISC-V Vector Extension (RVV), which is a key differentiator of RISC-V from other ISAs. RVV provides scalable and flexible vector capabilities, covering a wide range of applications from edge devices to HPC.
“I believe we are ahead of other architectures in using vector and matrix processing to support high-intensity numerical computing,” Asanović said. “Look at how we designed the vector ISA. I’m a bit biased because I led much of that work, but it is more scalable than vector extensions in other ISAs, which haven’t received much attention.”
Whether or not there is bias, the fact remains: RISC-V’s strength lies in its pure architecture, free from the constraints of traditional architectures. Combined with powerful vector and matrix extension capabilities, RISC-V CPUs can handle future demanding AI workloads without accelerators. GPUs and NPUs play important roles in AI, but today, CPUs are the key drivers of most AI processing.
The RISE project recently established a working group focused on AI/ML, creating a collaborative space to ensure widely used AI software (such as PyTorch CPU, Llama.cpp, GGML, LiteRT, OpenBLAS) maintains high performance on RISC-V hardware. In China, the Institute of Software, Chinese Academy of Sciences has quickly embraced RVV, bringing critical performance improvements to multimedia frameworks and open-source projects like ffmpeg, PipeWire, and Tesseract.
Waterman stated, “The growing focus on AI has also made it easier for RISC-V to catch up with its contemporaries. More and more software is emerging in the form of frameworks, which are more portable than a whole set of random software.”
As RISC-V’s performance improves, the ability to migrate AI workloads from the cloud to the edge also increases. ESWIN Computing is a company exploring these possibilities, recently running DeepSeek LLM natively on its RISC-V-based EIC77 series development boards.
Dr. He Ning, senior vice president and CTO of ESWIN, stated, “RISC-V enables us to innovate at the chip architecture level. Its open architecture facilitates deep collaboration between CPUs and AI accelerators (such as NPUs and TPUs). The architecture supports collaborative design for heterogeneous computing, effectively accelerating AI deployment at the edge. Additionally, it can provide different vector widths based on specific needs, allowing us to achieve higher levels of customization than ever before.”
“HPC is Right Around the Corner”
The approval of RVV v1.0 represents a significant breakthrough in the HPC field — European projects like the European Processor Initiative (EPI), EUPilot, and European RISC-V Digital Autonomy (DARE) are fully leveraging the advantages of this extension for supercomputing and other fields.
Waterman stated, “Given that we didn’t particularly hope for the ISA to be used outside Berkeley, the fact that others are trying to build supercomputers with RISC-V still shocks me.” However, these attempts are not only underway, but their ultimate success has made HPC one of the most exciting and unexpected frontier fields for this architecture.
Teresa Cervero, chief research engineer at the Barcelona Supercomputing Center (BSC), stated, “Today, RISC-V’s HPC capabilities are beyond doubt. Especially in the past five years, the performance gap between commercial RISC-V HPC platforms and more mature architectures is narrowing exponentially.”
Cervero stated that RISC-V offers a unique opportunity to redefine the future of HPC. “We must explore, leverage, and tap into its advantages over other architectures, rather than repeating what they have always done. Future supercomputers will be more heterogeneous and complex, and RISC-V brings the possibility of addressing this challenge in different ways.”
Cervero also painstakingly pointed out that I fell into the trap of equating HPC with supercomputers. In fact, she said, HPC is everywhere — any system capable of quickly processing complex tasks or massive data qualifies as HPC. One major frontier for HPC is the automotive industry, where the shift to software-defined vehicles (SDVs) requires flexible and scalable computing capabilities.
Software-Defined Vehicles
As the automotive industry evolves, RISC-V is making significant inroads into the future of automobiles. Its open, modular, and customizable design means that automakers can quickly adapt, reduce costs, and precisely build to their needs without being constrained by the roadmaps of other vendors. The ecosystem has provided FuSa-certified compilers, software development tools, and components for automotive applications, as well as rich operating systems and virtual platforms.
Perhaps most importantly, it enables automakers to shorten time-to-market. “The automotive industry has always been a very traditional industry,” Osier-Mixon said. “For automakers, the definition of rapid change is innovating every five to ten years.”
Thomas Schneid, senior director of software at Infineon Technologies, stated, “With the revolution of electric and electronic vehicles, this iteration needs to happen every two to three years. We need to significantly reduce complexity — architecture, software, connectivity, and networking — and lighten the weight of harnesses.”
I asked him how we could achieve this checklist. “Virtualization and standardization will be key,” Schneid continued. “RISC-V will enable Infineon to provide a scalable and cost-effective way to meet the diverse computing needs of future automotive microcontrollers, offering a single architecture for multiple processing cores and achieving reliability, scalability, and innovation through its open and inclusive nature.”
This segment requires reliable, secure, and dependable solutions based on the advantages of open-standard hardware and software. Schneid stated that the appeal of RISC-V is that we can achieve all of this with a single architecture. “This is a shift from proprietary closed solutions owned by a single entity to an environment built on close collaboration among many key market players.”
Establishing a high-performance automotive RISC-V reference platform in the coming years will reduce reliance on proprietary architectures and ensure long-term competitiveness. The Chips JU project TRISTAN and ISOLDE aim to promote the maturation and industrialization of the European RISC-V ecosystem, as well as a dedicated automotive RISC-V roadmap, serving as key drivers — coordinating stakeholders to build scalable, standards-based software and hardware platforms to meet Europe’s strategic needs in next-generation mobility.
Reaching for Outer Space
Supercomputers and self-driving cars are not the only targets for HPC. Last month, the European Space Agency (ESA) and Frontgrade Gaisler held a RISC-V Space Workshop in Gothenburg, focusing on the important role of RISC-V in space applications. Speakers from ESA, AMD, Thales, and other companies shared insights on HPC, AI, radiation-hardened systems, and open-source hardware, showcasing the architecture’s thriving momentum beyond Earth.
“Long ago, I foresaw that space would become one of RISC-V’s most compelling long-term use cases,” Asanović said in a speech titled “Instruction Set Hope to Break Free from Gravity” at the 2021 IEEE Space Computing Conference. “Decades-long missions require an ISA that won’t change or disappear. With RISC-V, if your spacecraft is still running 50 years from now, not only will the software tools continue to run, but they will also remain in active development with a strong ecosystem and community. This is the foundation needed for space computing and the goal we are working towards.”
Microchip’s product architecture and planning director Ted Speers stated, “From day one, Microchip has closely associated RISC-V with space.” Today, this connection has developed into a mature space-grade computing platform, and a $50 million contract for a high-performance space flight computing (HPSC) platform has been signed with NASA’s Jet Propulsion Laboratory (JPL).
The PIC64-HPSC SoC is built on multiple SiFive RISC-V cores and will provide radiation-hardened versions, built-in fault tolerance, post-quantum encryption, and vector acceleration for edge AI. What’s the goal? To redefine the infinite possibilities in orbit and beyond. Speers explained, “We are supporting a range of missions, from CubeSats to lunar landers, with unprecedented computing and fault tolerance capabilities in space systems. When you control the microarchitecture, you can do a lot to ensure its safety and prepare it for space applications.”
The PIC64-HPSC integrates SiFive’s RISC-V cores and is expected to be used in nearly all future space missions, including lunar and Martian surface missions. The architecture has already been validated in orbit — in 2022, a RISC-V-based Microchip PolarFire® SoC flight computer performed flawlessly during a nine-month run on the International Space Station (actually installed on the outside), marking an important milestone in the architecture’s transition from research lab to actual deployment.
Mars has entered the ecosystem’s sights. But for Speers, the bigger picture is propulsion. “Space is like a flywheel,” he said. “The more we leverage an open, adaptable platform like RISC-V, the faster we can drive toward the next frontier. I believe that by 2040, all commercial tech companies will have a space strategy.”
“Space continues to inspire many young people,” Frank Gürkaynak said. “One of our PhD students chose to join our team specifically after learning that he could work on space-related projects. This field aligns very well with our team’s strengths; in fact, our next generation of space-grade chips is about to go into production.”
Passing the Baton
Given the vast temporal and spatial gaps, it will ultimately be today’s youth who lead the way into orbit and beyond. Before that, we have a responsibility to establish a culture that attracts the next generation of innovators. In this regard, Frankwell Lin stated that the RISC-V ecosystem has far exceeded the sum of its semiconductor products. “For many engineers at Andes Technology, RISC-V is not just a platform, but a shared culture,” he said. “We are involved in every key working group, driving technical debates and helping approve the specifications that will shape future chips.”
This culture of openness, collaboration, and a strong focus on the future makes RISC-V not just a technical choice but a revolution. Like all great revolutions, its greatest impact may not be in what it has already achieved but in the changes it will bring in the next 15 years.
Fifteen years is a long time, both culturally and computationally. Looking back to 2010, you would find a world without USB, DVDs, or Java — the radio was playing “Gangsta’s Paradise,” and Amazon was a niche online bookstore. Many of RISC-V’s pioneers — seasoned veterans with long and successful careers — are still active in the industry, having given up their well-deserved rest to nurture this community. Some have moved on; others have sadly left us. Their legacy remains and is deeply embedded in what Redmond calls the “cornerstone of computing for generations to come” — architecture and code.
Today, this legacy is inspiring a new wave of innovators through projects like “One Chip, One Life” (OSOC) and “Thirty Hours to Design a Microprocessor” (MYTH). OSOC was launched by the University of Chinese Academy of Sciences in 2019, aiming to enable students to graduate with a fully self-designed RISC-V processor chip. OSOC aims to lower the barriers to RISC-V processor chip design through dynamic teaching that combines theory and practice, allowing more students to actively participate in every step of the design process, from concept to solving real problems. As of May 2025, OSOC has registered over 12,000 participants.
“Imagine what the next generation will achieve growing up in an environment where RISC-V is their native architecture in 15 years,” said Professor Bao Yungang, a researcher at the Institute of Computing Technology, Chinese Academy of Sciences. “My students can use a set of open and flexible toolsets to help them turn bold ideas into actual chips. That’s why I founded OSOC — to ensure that every student graduates with the ability to design their own RISC-V chip, experiencing the complete design cycle from conception to realization.”
American high school student and MYTH workshop graduate Sonit Sahoo was born just before RISC-V was established in 2010. He is one of the growing number of teenagers learning how computers work through RISC-V.
“When I was ten, I wrote a platform game for a Commodore64 emulator,” he explained. “I spent months on it. Unfortunately, I couldn’t get my hands on a real working Commodore emulator, and my excitement faded. Nevertheless, this project made me eager to build my own hardware to run my programs — which ultimately led me to find MYTH.”
The virtual MYTH workshop was co-hosted by semiconductor education technology company VSD and Redwood EDA, providing a structured introduction to the RISC-V architecture and covering concepts from software to hardware through practical labs.
“The future of our industry depends on early inspiration,” said Kunal Ghosh, co-founder of VSD. “If a 15-year-old can build a RISC-V processor at home using open-source tools, imagine what they might design 15 years from now. We’re not just teaching circuits — we’re fostering confidence, creativity, and the new generation of semiconductor innovators that the world desperately needs.”
“As part of the workshop, I built a custom floating-point extension for RISC-V,” Sahoo said. “It combined my love for number theory, programming, and hardware design, and truly helped me understand how computers are constructed.”
Sahoo stated that this feature is key to RISC-V’s strength. “From multinational corporations to hobbyists, anyone can build powerful, fully functional products with a very low barrier to entry. In 15 years, I hope to build a product with RISC-V that I and everyone who uses it can be proud of. A product that can have a lasting impact on humanity.”
For Frankwell Lin, this week is not just a milestone but a moment of validation. “RISC-V is ready, validated, and powerful. If you’re building the future, this is the platform you should rely on.”
“When I considered pursuing a PhD in computer architecture, I visited David Wheeler, the inventor of subroutine calls, at Cambridge University,” Asanović recalled. “He told me that there was nothing left to do in the field of computer architecture. If only he could see what we are doing now.”
We are building something larger and more significant than ever before. We are excited about the next 15 years. It is always evolving, always engaging, and it will not slow down. This story is just beginning.
END
Note: The cover image of this article is from freepik, self-made by the author, and publicly available media, all authorized.
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